Avaya Definity SI, Руководство по обслуживанию, Страница: 2381 / 2968

SYNC (Synchronization)
Issue 4 May 2002 10-1595 555-233-123
g. This error indicates that the slave Tone-Clock circuit pack is experiencing
loss of signal. Refer to note (i) for error resolution steps.
h. The following steps should be executed to resolve error 2049 and 2305:
1. Check for timing loops, and resolve any loops that exist.
2. Check the Error Log for any active as well as resolved Expansion
Interface circuit pack errors and refer to EXP-INTF (Expansion
Interface Circuit Pack) Maintenance documentation to resolve any
errors found.
3. High or Critical Reliability system:
■
Switch Tone-Clock circuit packs in the slave port network via
the set tone/clock PC system technician command. The
error count for this particular error should start decrementing
once the problem is solved—if the count does not decrease
in 15 minutes the problem still persists.
■
If the problem still persists, switch the Tone-Clock in the slave
port network back to the previous configuration. Then, switch
Expansion Interface Links via the set expansion-link PCSS
command.
■
If the problem still persists, switch the Expansion Interface
Links back to the previous configuration via the set
expansion-link PCSS. Then, switch the Tone-Clock circuit
packs in the master port network.
■
If the problem still persists, switch the Tone-Clock circuit
packs in the master port network back to the previous
configuration. If the system synchronization reference is a
Tone-Clock circuit pack, follow normal escalation procedures.
If the system synchronization reference is a DS1 interface
circuit pack, administer a different DS1 interface circuit pack
as the primary synchronization reference.
4. Standard system:—Error 2049:
■
Test the Tone-Clock circuit packs in the master and slave port
networks via the test tone/clock PC long command. Check
the Error Log for TDM-CLK errors and verify that TDM Bus
Clock Test #148 passes successfully. If Test #148 fails with
an Error Code 2 through 32, refer to “TDM-CLK” to resolve
the problem. If not, continue with the following steps.
■
If the master and slave Tone-Clock circuit packs do not fail
TDM Bus Clock Test #150 (PPM Inquiry), replace the
Expansion Interface circuit packs in the system.
■
If the system synchronization reference is a Tone-Clock
circuit pack and the master Tone-Clock circuit pack fails TDM
Bus Clock Test #150, follow the steps listed in “TDM-CLK” to
replace the master Tone-Clock circuit pack.