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SHDW-LNK (Memory Shadowing Link)
Issue 4 May 2002
10-1497
555-233-123
Shadow Link Test (#318)
Interactions
One interaction with the Standby SPE that results when testing the Memory
Shadowing Link is as follows:
If the Standby SPE is in Maintenance Mode because a previous test command on
a Standby SPE component was issued within the last three minutes, the Active
SPE takes the Standby SPE out of Maintenance Mode and puts it in Standby
Mode when the Shadow Link Test is run. Therefore, issuing another test
command on a Standby SPE component requires that the Standby SPE be put
into Maintenance Mode again before the test is run. Thus, the user notices a 1- to
20-minute delay when running another Standby SPE test after executing the
Shadow Link Test.
NOTE:
In most cases, the delay lasts only one to two minutes. However, a
20-minute delay is possible.
Another interaction that the Memory Shadowing Link has with the Standby SPE is
that if the Shadow Link Test fails, an error of type 67 is logged, and an alarm is
raised against the STBY-SPE (Standby SPE). This is because the failure of the
Shadow Link Test implies that Standby SPE Memory may not be an up-to-date
reflection of Active SPE Memory and, therefore, that the Standby SPE may not be
ready to take over as the Active SPE. Refer to “Hardware Error Log Entries and
Test to Clear Values” section of STBY-SPE (Standby SPE) Maintenance
documentation for more details.
Test Description
Because of the number and nature of steps that it performs, the Shadow Link Test
takes from 1 to 5 minutes to run, depending on the load that the system is
experiencing at the time. The Shadow Link Test performs the following activities to
verify the integrity of the Memory Shadowing Link:
286-based systems
■
Disables shadowing from Active SPE Memory (MEM-BD) to Standby SPE
Memory.
■
Requests the Standby SPE Maintenance/Tape Processor (PR-MAINT) to
release the Standby SPE processor (PROCR) for the Standby SPE
Processor to clear Standby SPE Memory (zero all memory locations).
■
Waits for Standby SPE Processor to report that Standby SPE Memory was
successfully cleared.
■
Requests the Standby SPE Maintenance/Tape Processor to hold the
Standby SPE processor reset.
Содержание Definity SI
Страница 1: ...0DLQWHQDQFH IRU YD D 1 7 6HUYHU 6 Volumes 1 2 and 3 555 233 123 Issue 4 May 2002...
Страница 62: ...Maintenance Architecture 555 233 123 1 26 Issue 4 May 2002...
Страница 92: ...Management Terminals 555 233 123 3 26 Issue 4 May 2002...
Страница 204: ...Routine Maintenance Procedures 555 233 123 5 100 Issue 4 May 2002...
Страница 250: ...LED Interpretation 555 233 123 7 10 Issue 4 May 2002...
Страница 2763: ...VC DSPPT Issue 4 May 2002 10 1977 555 233 123 Figure 10 107 VC Circuit Pack DSP Port Local TDM Loopback Test...
Страница 2776: ...Maintenance Object Repair Procedures 555 233 123 10 1990 Issue 4 May 2002 Figure 10 109 VC Circuit Pack Summer Port Loopback Test...
Страница 2804: ...Maintenance Object Repair Procedures 555 233 123 10 2018 Issue 4 May 2002...
Страница 2968: ...Index 555 233 123 IN 10 Issue 4 May 2002...