
SYNC (Synchronization)
Issue 4 May 2002
10-1593
555-233-123
Notes:
a. This error indicates a problem with the primary DS1 reference. It is cleared
when the primary reference is restored. The following steps should give an
indication of the source of the problem:
1. Check if the primary DS1 interface circuit pack is inserted in the
carrier via the list configuration board PCSS command.
2. Check the connection of the cable supplying the external timing
source to the primary DS1 interface circuit pack.
3. Test the primary DS1 interface circuit pack via the test board PCSS
long command. Check the Error Log for DS1-BD errors and refer to
the DS1-BD (DS1 Interface Circuit Pack) Maintenance
documentation to resolve any errors associated with the primary
DS1 interface circuit pack. If no errors are listed in the Error Log for
the primary DS1 interface circuit pack, continue with the following
steps.
4. Test the active Tone-Clock circuit pack in the master port network
via the test tone/clock PC long command. Check the Error Log for
TDM-CLK errors and verify that TDM Bus Clock Test #148 passes
successfully. If Test #148 fails with an Error Code 2 through 32, refer
to “TDM-CLK” to resolve the problem. If not, continue with the
following steps.
5. Execute the disable synchronization-switch and the enable
synchronization-switch commands. These two commands (when
executed together) switch the system synchronization reference to
the primary DS1 interface circuit pack. Check the Error Log and
execute the status synchronization command to verify that the
primary DS1 interface circuit pack is still the system synchronization
reference. If the primary DS1 interface circuit pack is not the system
synchronization reference, and this is not a High or Critical
Reliability system, continue with the following step.
6. High or Critical Reliability system:
Switch Tone-Clock circuit packs on the master port network via the
set tone/clock PC command, and repeat the disable/enable
commands described in the previous step.
b. This error indicates that Synchronization Maintenance has been disabled
via the disable synchronization-switch command. Execute the enable
synchronization-switch command to enable Synchronization
Maintenance reference switching and to resolve this alarm.
c. This error indicates a problem with the secondary DS1 reference. It is
cleared when the secondary reference is restored. Refer to note (a) to
resolve this error substituting secondary for primary in the preceding
resolution steps.
Содержание Definity SI
Страница 1: ...0DLQWHQDQFH IRU YD D 1 7 6HUYHU 6 Volumes 1 2 and 3 555 233 123 Issue 4 May 2002...
Страница 62: ...Maintenance Architecture 555 233 123 1 26 Issue 4 May 2002...
Страница 92: ...Management Terminals 555 233 123 3 26 Issue 4 May 2002...
Страница 204: ...Routine Maintenance Procedures 555 233 123 5 100 Issue 4 May 2002...
Страница 250: ...LED Interpretation 555 233 123 7 10 Issue 4 May 2002...
Страница 2763: ...VC DSPPT Issue 4 May 2002 10 1977 555 233 123 Figure 10 107 VC Circuit Pack DSP Port Local TDM Loopback Test...
Страница 2776: ...Maintenance Object Repair Procedures 555 233 123 10 1990 Issue 4 May 2002 Figure 10 109 VC Circuit Pack Summer Port Loopback Test...
Страница 2804: ...Maintenance Object Repair Procedures 555 233 123 10 2018 Issue 4 May 2002...
Страница 2968: ...Index 555 233 123 IN 10 Issue 4 May 2002...