
PROCR (Processor Circuit Pack)
Issue 4 May 2002
10-1423
555-233-123
Processor Sanity Timer Test (#83)
This test is destructive.
This test causes service to be disrupted for about seven seconds on the TN773
and for about one second on the TN786B. During this time, the system does not
respond to any user action.
This test checks to see if the 80286/386 processor watch-dog sanity timer is
functioning correctly. The processor intentionally allows the sanity timer to time
out. If the processor detects itself being reset, the test passes, and the processor
continues to execute normally. If the processor does not detect a reset, the test
has failed. If this test continues to fail, the processor pack should be replaced as
soon as possible. The sanity timer is not critical to system operation, but it is
needed for processor recovery if the processor stops functioning.
Table 10-536.
TEST #83 Processor Sanity Timer Test
Error
Code
Test
Result
Description/Recommendation
1000
ABORT
System software resources required for this test are not available.
1. Retry the command at 1-minute intervals a maximum of 5
times.
1029 2014
2015 2016
2017 2018
2020 2022
2024 2025
2051
ABORT
Refer to STBY-SPE Maintenance documentation for a description
of these error codes.
FAIL
The sanity timer did not time out as expected. The system
continues to function normally. If the processor gets into an
infinite loop, the reset CANNOT be detected, and the system
DOES NOT reboot itself to clear the problem.
1. Retry the command at 1-minute intervals a maximum of 5
times.
2. If test continues to fail, the Processor circuit pack should be
replaced as soon as possible. (Note that if you replace the
Processor circuit pack, you need to obtain a new license file.)
PASS
The sanity timer went off as expected. The system continues to
function normally. If the processor gets into an infinite loop, the
reset IS detected, and the system reboots itself to clear the
problem.
Continued on next page
Содержание Definity SI
Страница 1: ...0DLQWHQDQFH IRU YD D 1 7 6HUYHU 6 Volumes 1 2 and 3 555 233 123 Issue 4 May 2002...
Страница 62: ...Maintenance Architecture 555 233 123 1 26 Issue 4 May 2002...
Страница 92: ...Management Terminals 555 233 123 3 26 Issue 4 May 2002...
Страница 204: ...Routine Maintenance Procedures 555 233 123 5 100 Issue 4 May 2002...
Страница 250: ...LED Interpretation 555 233 123 7 10 Issue 4 May 2002...
Страница 2763: ...VC DSPPT Issue 4 May 2002 10 1977 555 233 123 Figure 10 107 VC Circuit Pack DSP Port Local TDM Loopback Test...
Страница 2776: ...Maintenance Object Repair Procedures 555 233 123 10 1990 Issue 4 May 2002 Figure 10 109 VC Circuit Pack Summer Port Loopback Test...
Страница 2804: ...Maintenance Object Repair Procedures 555 233 123 10 2018 Issue 4 May 2002...
Страница 2968: ...Index 555 233 123 IN 10 Issue 4 May 2002...