Avaya Definity SI, Руководство по обслуживанию, Страница: 2380 / 2968

Maintenance Object Repair Procedures
555-233-123 10-1594 Issue 4 May 2002
d. This error indicates that the Tone-Clock circuit pack is providing the timing
source for the system. The primary and secondary (if administered) are not
providing a valid timing signal. Investigate errors 1 and 257 to resolve this
error.
e. This error indicates that the external Stratum 3 Clock fails to provide the
system timing reference. Refer to Stratum 3 Clock Maintenance document
to resolve the defective synchronization reference.
This error indicates excessive switching of system synchronization
references has occurred. When this error occurs, synchronization is
disabled and the Tone-Clock circuit pack (in the master port network)
becomes the synchronization reference for the system. Execute the
following steps to resolve this error:
1. Check for timing loops and resolve any loops that exist.
2. Test the active Tone-Clock circuit pack in the master port network
via the test tone/clock PC long command. Check the Error Log for
TDM-CLK errors and verify that TDM Bus Clock Test #148 passes
successfully. If Test #148 fails with an Error Code 2 through 32, refer
to the TDM-CLK (TDM Bus Clock) Maintenance documentation to
resolve the problem. If not, continue with the following steps.
3. High or Critical Reliability system: Switch Tone-Clock circuit
packs on the master port network via the set tone/clock PC
command.
Standard system: Replace the primary and secondary (if
administered) DS1 Interface circuit packs.
4. Check for an error logged against the primary or secondary DS1
board. If there is an error, follow the DS1 section to resolve the
errors. If there is not, enter enable sync, and wait for two to five
minutes for the primary sync source to come on-line.
In Release 5si + memory: This error indicates that some reference
switches have occurred. If there is not a major SYNC alarm, then
investigate other SYNC errors. If there is an active major SYNC
alarm, and if this is not a Stratum 3 system, then follow the steps
above.
f. This error indicates that the Expansion Interface Link is experiencing timing
slips. The two port networks are not synchronized. This error increases the
bit error rates for data transmission between port networks. Verify that all
the TDM/LAN Bus cables on the backplane are AT&T Parts number AT&T
SK00199-001 rather than flat ribbon cables. Also, check that the bus
terminators are the ZAHF V1 TDM/LAN Bus Terminator type. Refer to note
(i) for error resolution steps.
This error is cleared by a leaky bucket strategy and takes one hour to clear
(leak away) the error counter once it is alarmed. Therefore, it may take up
to one hour to clear the alarm after the problem is cleared.