NXP Semiconductors MPC5644A, Reference Manual, Page: 885 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 885
NOTE
If the ETPU_TBCR field TCRCF selects the filter clock of the channels (see
Section 24.4.3.1, ETPU_TBCR – eTPU Time Base Configuration
Register
), the TCRCLK filter will be clocked as if FCSS = 0 always
dividing system clock /2 using FPSCK, regardless if FCSS is 0 or 1.
24.5.5.7 Channel Timing Modes
Channels can work on two different timing schemes, defining the period of channel clocking, tied to T2
and T4 microengine phases, as explained in subsections below. Microengine T2 and T4 phases are shown
in
Section 24.7.1, Microcycle and I/O timing .
24.5.5.7.1 T2 Channel Timing
In T2 timing mode the channel event state can only be updated every two system clocks (see Figure 24-75 ).
Pin state, TDLs, MRLs and Capture registers are updated on the microengine’s T2 clock phase. MRLE
clears also happen on T2, but MRLE setting occurs on T4, together with the Match register write by
microcode (see
Section 24.5.9.3.5, Write Channel Match and UDCM Registers ).
Channels work in T2 timing mode when all the following conditions are true:
• ETPU_TBCR bit TCR1CS is 0 (see Section 24.4.3.1, ETPU_TBCR – eTPU Time Base
Configuration Register ).
• the Enhanced Digital Filter is not configured as bypass (see Section 24.5.5.6, Enhanced Digital
Filter – EDF ).
• ETPU_ECR bit FCSS is 0 (see Section 24.5.5.6.5, Filter Clock Prescaler ).
24.5.5.7.2 T2/T4 Channel Timing
In T2/T4 timing mode the channel event state can be updated on any system clock (see Figure 24-76 ). Pin
state, TDLs, MRLs, MRLEs, and Capture registers are updated either on microengine’s T2 or T4 clock
phases. MRLE clears can happen on T2 or T4, but MRLE setting occurs on T4 only, together with the
Match register write by microcode (see
Section 24.5.9.3.5, Write Channel Match and UDCM Registers ).
Channels work in T2/T4 timing mode when either one the following conditions are true:
• ETPU_TBCR bit TCR1CS is 1 (see Section 24.4.3.1, ETPU_TBCR – eTPU Time Base
Configuration Register ).
• the Enhanced Digital Filter is configured as bypass (see Section 24.5.5.6, Enhanced Digital Filter
– EDF ).
• ETPU_ECR bit FCSS is 1 (see Section 24.5.5.6.5, Filter Clock Prescaler ).
24.5.6 Time Bases
Each eTPU engine has two Time Counter Registers, TCR1 and TCR2. They provide 24-bit time bases,
shared by all 32 channels. Any channel can use both time bases to:
2
Integrator mode is available for TCRCLK filtering only, see Section 24.5.6.5, TCRCLK digital filter .