NXP Semiconductors MPC5644A, Reference Manual, Page: 269 / 1735

Memory Protection Unit (MPU)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 269
13.4.2.5 MPU Region Descriptor Alternate Access Control n (MPU_RGDAACn)
As noted in Section 13.4.2.4.3, MPU Region Descriptor n, Word 2 (MPU_RGDn.Word2) , it is expected
that because system software may adjust the access controls within a region descriptor
(MPU_RGD
n .Word2) only as different tasks execute, an alternate programming view of this 32-bit entity
is desired. If only the access controls are being updated, this operation should be performed by writing to
MPU_RGDAAC
n (alternate access control n ) as stores to these locations do not affect the descriptor’s
valid bit.
The memory address therefore provides an alternate location for updating MPU_RGD n .Word2.
Because the MPU_RGDAAC n register is another memory mapping for MPU_RGD n .Word2, the field
definitions shown in Table 13-10 are identical to those presented in Table 13-8 .
8–15
PIDMAS
K
Process Identifier Mask
This 8-bit field provides a masking capability so that multiple process identifiers can be included as part
of the region hit determination. If a bit in the PIDMASK is set, the corresponding bit of the PID is ignored
in the comparison. This field is combined with the PID and included in the region hit determination if
MPU_RGD
n .Word2[MxPE] is set. For more information on the handling of the PID and PIDMASK, see
Section 13.5.1.1, Access Evaluation—Hit Determination .
31
VLD
Valid
This bit signals the region descriptor is valid. Any write to MPU_RGD
n .Word{0,1,2} clears this bit, but a
write to MPU_RGD n .Word3 sets or clears this bit depending on bit 31 of the write operand.
0 Region descriptor is invalid
1 Region descriptor is valid
Address: MPU_BASE (0xFFF1_0000) + 0x800 + (4* n ) (MPU_RGDAAC n ) Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
M7
RE
M7WE
M6
RE
M6WE
0 0
M4
RE
M4WE
0 0 0 0 0 0 0 0
W
Reset – – – – – – – – – – – – – – – –
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0
M0PE
M0SM
M0UM
W r w x
Reset – – – – – – – – – – – – – – – –
= not implemented
Figure 13-8. MPU RGD Alternate Access Control n (MPU_RGDAACn)
Table 13-9. MPU_RGDn Word 3 field description (continued)
Field Description