NXP Semiconductors MPC5644A, Reference Manual, Page: 156 / 1735

Enhanced Direct Memory Access Controller (eDMA)
MPC5644A Microcontroller Reference Manual, Rev. 6
156 Freescale Semiconductor
8.3.2.7 eDMA Set Enable Error Interrupt Register (EDMA_SEEIR)
The EDMA_SEEIR provides a memory-mapped mechanism to set a given bit in the EDMA_EEIRH or
EDMA_EEIRL to enable the error interrupt for a given channel. The data value on a register write causes
the corresponding bit in the EDMA_EEIRH or EDMA_EEIRL to be set. Setting bit 1 (SEEI[0]) provides
a global set function, forcing the entire contents of EDMA_EEIRH or EDMA_EEIRL to be asserted.
Reads of this register return all zeroes.
If bit 0 is set, the SEEI command is ignored. This allows multiple byte registers to be written as a 32-bit
word. Reads of this register return all zeroes.
Offset: EDM 0x0019 Access: User write-only
0 1 2 3 4 5 6 7
R
W NOP CERQ[0:6]
Reset 0 0 0 0 0 0 0 0
Figure 8-9. eDMA Clear Enable Request Register (EDMA_CERQR)
Table 8-8. EDMA_CERQR field descriptions
Field Description
0
NOP
No operation
0 Normal operation
1 No operation, ignore bits 1–7.
1–7
CERQ[0:6]
Clear Enable Request
0–32 (64 for eDMA) Clear corresponding bit in EDMA_ERQRH or EDMA_ERQRL.
64–127
Clear all bits in EDMA_ERQRH and EDMA_ERQRL.
Offset: EDM 0x001A Access: User write-only
0 1 2 3 4 5 6 7
R
W NOP SEEI[0:6]
Reset 0 0 0 0 0 0 0 0
Figure 8-10. eDMA Set Enable Error Interrupt Register (EDMA_SEEIR)
Table 8-9. EDMA_SEEIR field descriptions
Field Description
0
NOP
No operation
0 Normal operation
1 No operation, ignore bits 1–7.
1–7
SEEI[0:6]
Set Enable Error Interrupt
0–32 (64 for eDMA) Set corresponding bit in EDMA_EIRRH or EDMA_EIRRL.
64–127
Set all bits in EDMA_EIRRH or EDMA_EEIRL.