NXP Semiconductors MPC5644A, Reference Manual, Page: 264 / 1735

Memory Protection Unit (MPU)
MPC5644A Microcontroller Reference Manual, Rev. 6
264 Freescale Semiconductor
13.4.2.4 MPU Region Descriptor n (MPU_RGDn)
Each 128-bit (16-byte) region descriptor specifies a given memory space and the access attributes
associated with that space. The descriptor definition is fundamental to the operation of the MPU.
The region descriptors are organized sequentially in the MPU’s programming model and each of the four
32-bit words are detailed in the subsequent sections.
13.4.2.4.1 MPU Region Descriptor n, Word 0 (MPU_RGDn.Word0)
The first word of the MPU region descriptor defines the 0-modulo-32 byte start address of the memory
region. Writes to this word clear the region descriptor’s valid bit.
24–27
EMN
Error Master Number
This 4-bit read-only field records the logical master number of the faulting reference. This field is used to
determine the bus master that generated the access error.
28–30
EATTR
Error Attributes
This 3-bit read-only field records attribute information about the faulting reference. The supported
encodings are defined as:
000 User mode, instruction access
001 User mode, data access
010 Supervisor mode, instruction access
011 Supervisor mode, data access
All other encodings are reserved. For non-core bus masters, the access attribute information is typically
wired to supervisor, data (0b011).
31
ERW
Error Read/Write
This 1-bit read-only field signals the access type (read, write) of the faulting reference.
0 Read
1 Write
Address: MPU_BASE (0xFFF1_0000) + (16* n ) + 0x0 (MPU_RGD n .Word0) Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R SRTADDR[26:11]
W
Reset – – – – – – – – – – – – – – – –
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R SRTADDR[10:0]
W
Reset – – – – – – – – – – – 0 0 0 0 0
= not implemented
Figure 13-4. MPU Region Descriptor n, Word 0 Register (MPU_RGDn.Word0)
Table 13-5. MPU_EDRn field descriptions (continued)
Field Description