NXP Semiconductors MPC5644A, Reference Manual, Page: 1096 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
1096 Freescale Semiconductor
Interrupt Status Registers (EQADC_FISR) , is not decremented by one, and Transfer Next Data Pointer 0
is incremented by one (or wrapped around) to point to the next entry in the CFIFO0.
Figure 25-62. CFIFO0 in Streaming Mode Diagram
The detailed behavior of the Push Next Data Pointer and Transfer Next Data Pointer is described in the
example shown in
Figure 25-63 where a CFIFO with 16 entries is shown for clarity of explanation, the
actual hardware implementation has only four/eight entries. In this example, CFIFO0 with 16 entries is
shown in sequence after pushing and transferring entries.
32-bit Entry 1
32-bit Entry 2
--------------------
--------------------
Push Next
Data Pointer *
Transfer Next
Data Pointer *
CFIFO
Push Register
CFIFO
Control Logic
DMA Done
Interrupt/DMA Request
Control
Signals
Data to
external
device or
to on-chip
ADCs
Transfer Counter
* All CFIFO entries are memory mapped and the
entries addressed by these pointers can have their
absolute addresses calculated using TNXTPTR and
CFCTR.
Repeat
Pointer
32-bit Entry n, Rep
Write to slave-bus
interface by CPU or
DMA