NXP Semiconductors MPC5644A, Reference Manual, Page: 614 / 1735

Software Watchdog Timer (SWT)
MPC5644A Microcontroller Reference Manual, Rev. 6
614 Freescale Semiconductor
SWT_MCR is set then the SWT generates a system reset on an invalid access otherwise a bus error is
generated. If either the HLK or SLK bits in the SWT_MCR are set then the SWT_MCR, SWT_TO,
SWT_WN, SWT_SK registers are read-only.
20.3.1 Memory map
The SWT memory map is shown in Table 20-1 . The reset values of SWT_MCR, SWT_TO and SWT_WN
are device specific. These values are determined by SWT inputs.
20.3.2 Register descriptions
The following sections detail the individual registers within the SWT programming model.
20.3.2.1 SWT Module Control Register (SWT_MCR)
The SWT_MCR contains fields for configuring and controlling the SWT. The reset value of this register
is device specific. Some devices can be configured to automatically clear the SWT_MCR[WEN] bit
during the boot process. This register is read-only if either the SWT_MCR[HLK] or SWT_MCR[SLK]
bits are set.
Table 20-1. SWT memory map
Offset from SWT
Base address
(0xFFF3_8000)
Register name Register description
Size
(bits)
Access Location
0x0000 SWT_MCR SWT Module Control Register 32 R/W on page
20-614
0x0004 SWT_IR SWT Interrupt Register 32 R/W on page
20-616
0x0008 SWT_TO SWT Time-out Register 32 R/W on page
20-616
0x000C SWT_WN SWT Window Register 32 R/W on page
20-617
0x0010 SWT_SR SWT Service Register 32 R/W on page
20-617
0x0014 SWT_CO SWT Counter Output Register 32 R on page
20-618
0x0018 SWT_SK SWT Service Key Register 32 R/W on page
20-618
0x001C – 0x3FFF Reserved — — —