NXP Semiconductors MPC5644A, Reference Manual, Page: 1425 / 1735

FlexCAN Module
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1425
When the frame is received, it is temporarily stored in a hidden auxiliary message buffer called Serial
Message Buffer (SMB). The matching process takes place during the CRC field of the received frame. If
a matching ID is found in the FIFO table or in one of the regular message buffers, the contents of the SMB
will be transferred to the FIFO or to the matched message buffer during the 6th bit of the End-Of-Frame
field of the CAN protocol. This operation is called “move-in”. If any protocol error (CRC, ACK, etc.) is
detected, than the move-in operation does not happen.
For the regular mailbox message buffers, a message buffer is said to be “free to receive” a new frame if
the following conditions are satisfied:
• The message buffer is not locked (see Section 32.5.6.3, Message buffer lock mechanism )
• The Code field is either EMPTY or else it is FULL or OVERRUN but the CPU has already serviced
the message buffer (read the C/S word and then unlocked the message buffer)
If the first message buffer with a matching ID is not “free to receive” the new frame, then the matching
algorithm keeps looking for another free message buffer until it finds one. If it can not find one that is free,
then it will overwrite the last matching message buffer (unless it is locked) and set the Code field to
OVERRUN (refer to
Table 32-5 and Table 32-6 ). If the last matching message buffer is locked, then the
new message remains in the SMB, waiting for the message buffer to be unlocked (see Section 32.5.6.3,
Message buffer lock mechanism ).
Suppose, for example, that the FIFO is disabled and there are two message buffers with the same ID, and
FlexCAN starts receiving messages with that ID. Let us say that these message buffers are the second and
the fifth in the array. When the first message arrives, the matching algorithm will find the first match in
MB number 2. The code of this message buffer is EMPTY, so the message is stored there. When the second
message arrives, the matching algorithm will find MB number 2 again, but it is not “free to receive”, so it
will keep looking and find MB number 5 and store the message there. If yet another message with the same
ID arrives, the matching algorithm finds out that there are no matching message buffers that are “free to
receive”, so it decides to overwrite the last matched message buffer, which is number 5. In doing so, it sets
the Code field of the message buffer to indicate OVERRUN.
The ability to match the same ID in more than one message buffer can be exploited to implement a
reception queue (in addition to the full featured FIFO) to allow more time for the CPU to service the
message buffers. By programming more than one message buffer with the same ID, received messages will
be queued into the message buffers. The CPU can examine the Time Stamp field of the message buffers
to determine the order in which the messages arrived.
The matching algorithm described above can be changed to be the same one used in previous versions of
the FlexCAN module. When the MBFEN bit in MCR is negated, the matching algorithm stops at the first
message buffer with a matching ID that it founds, whether this message buffer is free or not. As a result,
the message queueing feature does not work if the MBFEN bit is negated.
Matching to a range of IDs is possible by using ID Acceptance Masks. FlexCAN supports individual
masking per message buffer. Please refer to
Section 32.4.5.13, Rx Individual Mask Registers
(RXIMR0–RXIMR63) . During the matching algorithm, if a mask bit is asserted, then the corresponding
ID bit is compared. If the mask bit is negated, the corresponding ID bit is “don’t care”. Please note that the
Individual Mask Registers are implemented in RAM, so they are not initialized out of reset. Also, they can
only be programmed if the MBFEN bit is asserted and while the module is in Freeze Mode.