NXP Semiconductors MPC5644A, Reference Manual, Page: 1206 / 1735

Decimation Filter
MPC5644A Microcontroller Reference Manual, Rev. 6
1206 Freescale Semiconductor
26.5.6 IIR and FIR filter
This section describes the IIR filters implemented in the Decimation Filter block. Figure 26-16 shows the
filters functional diagrams. The figure shows a IIR filter of fourth order (4 poles). The filter topology, not
the hardware, is represented. The hardware implementation is based on a MAC unit controlled by an FSM
which implements the filter algorithm.
Figure 26-16. 1 x 4 poles IIR filter functional diagram
The difference equation for the IIR filter of Figure 26-16 can be written as:
Eqn. 26-1
where x(n) is the filter input at time n, y(n) is the filter output at time n , N is the number of feed-forward
filter coefficients minus one, B
i
are the feed-forward filter coefficients, M is the number of feed-back filter
coefficients, and A
j
are the feedback filter coefficients.
Equation 26-1 can be written as:
Eqn. 26-2
y(n)
Z
-1
Z
-1
Z
-1
Z
-1
+
+
+
+
B
0
Z
-1
Z
-1
Z
-1
Z
-1
+
+
+
+
x(n)
A
4
A
3
A
2
A
1
B
4
B
3
B
2
B
1
x(n-1)
y(n-1)
x(n-2)
x(n-3)
x(n-4)
y(n-2)
y(n-3)
y(n-4)
y n
 
B
i
x n i –
 
A
j
y n j –
 
j 1 =
M

+
i 0 =
N

=
w n
 
B
i
S
-----
x n i –
 
i 0 =
N

=