NXP Semiconductors MPC5644A, Reference Manual, Page: 1370 / 1735

Enhanced Serial Communication Interface (ESCI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1370 Freescale Semiconductor
31.4.5.3.5 Loop mode
In Loop Mode, the input of the receiver is driven by the output of the transmitter. The RXD pin is
disconnected from the eSCI module.
Figure 31-30. Loop Mode
31.4.5.3.6 Frame and character reception
The receiver is started when it is in Ready or Wake-up state and on the selected receiver input (see
Section 31.4.5.3.2, Receiver input mode selection ”) an active signal is sampled. The receiver enters the
Run or Wake-up state. The received bits are recovered by the bit sampling described in
Section 31.4.5.3.13, Bit sampling ”. During the reception, the received bits are shifted into the internal shift
register.
31.4.5.3.7 Break character detection
The receiver does not provide any means to detect the reception of a break character. Instead, break
characters are processed as data frames. Due to the received 0 at the stop bit location, the reception of a
break character causes at least a framing error. The error reporting is performed as described in
Section 31.4.5.4, Reception error reporting ”.
31.4.5.3.8 Idle character detection
The Idle character detection starts after the reception of the last stop bit.
31.4.5.3.9 CPU controlled SCI data frame reception
This section describes the reception process when the receiver is in the Run state.
When the required number of frame bits have been received, the payload bits of the received frame are
transferred into
SCI data register (eSCI_DR) if the RDRF flag is 0. The receive data register full flag
RDRF in Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set. If the receive interrupt enable bit RIE
in the Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set, the RDRF interrupt request is generated.
If an idle character has been detected, the IDLE flag in the Interrupt Flag and Status Register 1
(eSCI_IFSR1) is set. If the idle line interrupt enable bit ILIE in the Control register 1 (eSCI_CR1) is set,
the IDLE interrupt request is generated.
If any of the receiver errors described in Section 31.4.5.4, Reception error reporting ” have been occurred,
that corresponding flags will be set.
TRANSMITTER
RECEIVER RXD
TXD