NXP Semiconductors MPC5644A, Reference Manual, Page: 656 / 1735

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5644A Microcontroller Reference Manual, Rev. 6
656 Freescale Semiconductor
UCPRE Prescaler
The UCPRE bits select the clock divider value for the internal prescaler of the channel controlled by
this register.
UCPREN Prescaler Enable
The UCPREN bit enables the prescaler counter.
0 Prescaler disabled (no clock) and prescaler counter is loaded with UCPRE value
1 Prescaler enabled
DMA Direct Memory Access
The DMA bit selects whether the FLAG generation (see
Section 22.4.3.5, eMIOS200 Channel
Status Register (EMIOS_CSR[n]) ) is used as an interrupt or as a DMA request.
0 FLAG/overrun assigned to interrupt request
1 FLAG/overrun assigned to DMA request
IF Input Filter
The IF bits control the programmable input filter, selecting the minimum input pulse width that can
pass through the filter. For output modes, these bits have no meaning.
FCK Filter Clock Select
The FCK bit selects the clock source for the programmable input filter.
0 Prescaled clock
1 Main clock
Table 22-8. EMIOS_CCR field description (continued)
Field Description
UCPRE Divide ratio
00 1
01 2
10 3
11 4
IF
1
1
Filter latency is three clock edges.
Minimum input pulse width
[FLT_CLK periods]
0000 Bypassed
2
2
The input signal is synchronized before arriving to the digital filter.
0001 02
0010 04
0100 08
1000 16
All others Reserved