NXP Semiconductors MPC5644A, Reference Manual, Page: 844 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
844 Freescale Semiconductor
24.5.5.1 Channel Registers and Flags
Channel configuration and control registers can be divided in the following groups:
• Host Configuration and Control registers , which define channel Function and parameter
allocation in SPRAM, input signal filtering, manage Host interrupts, and are used for Host Service
Requests; they can only be accessed by Host, except for the Function Mode bits which can be also
tested by microcode.
• Event Registers , which can only be accessed by eTPU Microengine, through dedicated Channel
Control microinstruction operations (see Section 24.5.9.3, Channel control and configuration
microoperations ); these registers are directly used to implement channel functionality, and include
channel event status latches which can be directly tested by Microengine branch instructions.
• Pin Control registers , which basically define pin state and transition polarity (but not input signal
filtering); they are accessible only by dedicated Channel Control microinstruction operations.
• Link registers , which implement the channel link mechanism that allows one channel to request
service to another one; they are accessible only by microinstruction operations.
• General Channel registers : CHAN, SRI, Flag0/1, PDCM, UDCM.
Most of those registers are channel exclusive, i.e., there is one copy of them for each channel. Microcode
can access registers from only one channel at a time. The Channel Selection (CHAN) register (see
Section ,
Channel Selection Register – CHAN ), accessible only by microcode, defines the channel whose registers
are being accessed, with exception of link register and function mode. CHAN register assumes the value
of the channel to be serviced at the beginning of TST.
The Service Request Inhibit (SRI) register controls the generation of Service Requests on matches and
transitions, also affecting channel logic behavior. For a full description see
Section , SRI –
Match/Transition Service Request Inhibit Latch . Flag0/1 are used to select channel service threads based
on channel software state. See Section , Flag1,Flag0 – Channel “state resolution” flags , for more details.
Host Configuration and Control registers are described in Section 24.4.7, Channel configuration and
control registers .
Time Base configuration is common to all channels, and described in Section 24.5.6, Time Bases . Time
Base selection for matches and captures, however, is individual to each channel, and is part of the Event
Registers.
Link registers are described in Section 24.5.5.5, Channel Link .
The following sections describe the Event Registers and Pin Control registers.
24.5.5.1.1 ER – Event Registers
Each channel contains two identical Event Register sets, named ERA and ERB, corresponding to the two
actions supported. Each Event Register set contains:
• A 24-bit Match register (Match A or Match B), which holds a match value. This value is compared
against the selected match time base (TCR1 or TCR2).
• A 24-bit Capture register (CaptureA or CaptureB), which samples the selected capture time base
(TCR1 or TCR2)