NXP Semiconductors MPC5644A, Reference Manual, Page: 1540 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
1540 Freescale Semiconductor
Figure 33-118. Example of FlexRay memory area layout (FR_MCR[FAM] = 1)
33.6.4.3 Message buffer header area (FR_MCR[FAM] = 0)
The message buffer header area contains all message buffer header fields of the physical message buffers
for all message buffer types. The following rules apply to the message buffer header fields for the three
type of message buffers.
1. The start byte address SADR_MBHF of each message buffer header field for individual message
buffers and receive shadow buffers must fulfill Equation 33-6 .
SADR_MBHF = (i * 10) + FR_SYMBADR[SMBA]; (0 < i < 256) Eqn. 33-6
2. The start byte address SADR_MBHF of each message buffer header field for the FIFO must fulfill
Equation 33-7 .
SADR_MBHF = (i * 10) + FR_SYMBADR[SMBA]; (0 < i < 1024) Eqn. 33-7
FIF
O
H
eader Ar
ea
F
IFO
Fl
ex
R
a
y Me
mo
ry
Data Field Offset Frame Header Slot Status
Data Field Offset Frame Header Slot Status
Message Buffer Header Fields
Receive FIFO A
Data Field Offset Frame Header Slot Status
Data Field Offset Frame Header Slot Status
Message Buffer Header Fields
Receive FIFO B
FR_RFSYMBADR[SMBA]
System Memory
Messag
e Buffer H
eader Ar
ea
F
lexRay
Memory
Message Buffer Data Area
Sync Frame Table Area
Data Field Offset Frame Header Slot Status
Data Field Offset Frame Header Slot Status
Message Buffer Header Fields
Individual Message Buffers
Receive Shadow Buffers
Data Field Offset Frame Header Slot Status
10 bytes
FR_SYMBADR[SMBA]
FIFO Message Buffer Data Area