NXP Semiconductors MPC5644A, Reference Manual, Page: 731 / 1735

Reaction Module (REACM)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 731
23.5.3.4 Module initialization
To execute the modulation process the Reaction Module must be initialized with a correct sequence. One
method is described as follows:
1. Make sure eTPU channels are at zero, inactive state.
2. Set up eQADC module.
3. Program the Modulation Words.
4. Program the Threshold Bank.
5. Program the Shared Timer Bank.
6. Program the Holdoff Timer Bank.
7. Program Timer Configuration register.
8. Program the Module Configuration register.
9. Program the Channel Router register.
10. Program the Channel Configuration register.
11. Start eTPU channels.
It is important to notice that the channel activation, by setting CHEN = 01, should be done after all other
registers have been configured and before the input timer control signals are active. Violating this order
may lead to errors when the modulation cycle is executed by the channel.
NOTE
If a glitch is introduced in the input timer control pulse, the channel stops to
modulate and does not operate during the pulse just after the glitch. The
glitch value for wrong operation ranges from 1 system clock to about 5
times the number of channels.
23.6 Monitored modulation
The modulation executed by the reaction channel can be monitored by measuring the width of the PWM
pulses provided by the channel. If the pulse becomes too narrow it means that the load impedance is
probably too low, thus indicating a possible short circuit. If the PWM pulses become too wide it may
indicate an open circuit on the solenoid.
The limits for narrow and wide pulses are defined by RANGE_PWD and MIN_PWD registers (see
Figure 23-16 and Figure 23-17 ). These values apply to all reaction channels. The PWM pulses are
measured by the Hold-off timers within the reaction channels. This is possible only during idle periods of
this timer, for example from the moment a hold-off timeout occurs until the maximum threshold is reached
when HOD is being used for the channel output pins. During this period the hold-off counter is not used
and thus it can measure pulse widths and compare them against predefined limits defined by
RANGE_PWD and MIN_PWD registers, as shown in
Figure 23-31 .
NOTE
Consider an uncertainty of (+1) in the value MIN_PWD and (M
RANGE_PWD) when calculating the pulse width limits. The Hold-off
prescaler contributes to this uncertainty.