NXP Semiconductors MPC5644A, Reference Manual, Page: 157 / 1735

Enhanced Direct Memory Access Controller (eDMA)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 157
8.3.2.8 eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR)
The EDMA_CEEIR provides a memory-mapped mechanism to clear a given bit in the EDMA_EEIRH or
EDMA_EEIRL to disable the error interrupt for a given channel. The data value on a register write causes
the corresponding bit in the EDMA_EEIRH or EDMA_EEIRL to be cleared. Setting bit 1 (CEEI[0])
provides a global clear function, forcing the entire contents of the EDMA_EEIRH or EDMA_EEIRL to
be zeroed, disabling error interrupts for all channels. Reads of this register return all zeroes.
If bit 0 is set, the CEEI command is ignored. This allows multiple byte registers to be written as a 32-bit
word. Reads of this register return all zeroes.
8.3.2.9 eDMA Clear Interrupt Request Register (EDMA_CIRQR)
The EDMA_CIRQR provides a memory-mapped mechanism to clear a given bit in the EDMA_IRQRH
or EDMA_IRQRL to disable the interrupt request for a given channel. The given value on a register write
causes the corresponding bit in the EDMA_IRQRH or EDMA_IRQRL to be cleared. Setting bit 1
(CINT[0]) provides a global clear function, forcing the entire contents of the EDMA_IRQRH or
EDMA_IRQRL to be zeroed, disabling all eDMA interrupt requests. Reads of this register return all
zeroes.
If bit 0 is set, the CINT command is ignored. This allows multiple byte registers to be written as a 32-bit
word. Reads of this register return all zeroes.
Offset: EDM 0x001B Access: User write-only
0 1 2 3 4 5 6 7
R
W NOP CEEI[0:6]
Reset 0 0 0 0 0 0 0 0
Figure 8-11. eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR)
Table 8-10. EDMA_CEEIR field descriptions
Field Description
NOP No operation
0 Normal operation
1 No operation, ignore bits 1-7.
CEEI[0:6] Clear Enable Error Interrupt
0–32 (64 for eDMA) Clear corresponding bit in EDMA_EEIRH or EDMA_EEIRL.
64–127
Clear all bits in EDMA_EEIRH or EDMA_EEIRL.