NXP Semiconductors MPC5644A, Reference Manual, Page: 552 / 1735

System Integration Unit (SIU)
MPC5644A Microcontroller Reference Manual, Rev. 6
552 Freescale Semiconductor
Figure 16-219. Core MMU PID Control Register (SIU_EMPCR0)
16.7 Functional description
The following sections provide an overview of the SIU operation features.
SI 0x9B4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
EXT_PID_
E
N
EXT_
P
ID
_SYN
C0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0
EXT_
P
ID
6
EXT_
P
ID
7
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Table 16-220. SIU_EMPCR0 field description
Field Description
EXT_PID_EN
0
External PID Selection Enable
0: The contents of this register are not used to select the alternate MMU mapping.
1: The contents of this register are used to select the alternate MMU mapping defined by
EXT_PID6 and EXT_PID7.
EXT_PID_SYNC0
1
External PID Synchronization 0
0: The Nexus Watchpoint Event 2 does not transfer the EXT_PID6 and EXT_PID7 values to
the MMU.
1: The Nexus Watchpoint Event 2 transfers the EXT_PID6 and EXT_PID7 values to the
MMU.
2:29 Reserved
EXT_PID6
30
External PID bit 6
0: When the PID remapping is enabled (EXT_PID_EN = 1), the processor MMU’s PID
register bit 6 is logic 0.
1: When the PID remapping is enabled (EXT_PID_EN = 1), the processor MMU’s PID
register bit 6 is logic 1.
EXT_PID7
31
External PID bit 7
0: When the PID remapping is enabled (EXT_PID_EN = 1), the processor MMU’s PID
register bit 7 is logic 0.
1: When the PID remapping is enabled (EXT_PID_EN = 1), the processor MMU’s PID
register bit 7 is logic 1.