NXP Semiconductors MPC5644A, Reference Manual, Page: 778 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
778 Freescale Semiconductor
12 FCSS—Filter Clock Source Selection
Speeds up the filter clock source before the prescaler, allowing more input capture resolution at minimum
prescaling.
1: use system clock as EDF clock source before prescaler
0: use system clock / 2 as EDF clock source before prescaler.
Note: FCSS = 1 also makes the channel work on T2/T4 timing mode (see Section 24.5.5.7.2, T2/T4
Channel Timing ).
13-15 FPSCK[2:0]—Filter Prescaler Clock Control
FPSCK controls the prescaling of the clocks used in digital filters for the channel input signals and
TCRCLK input, as shown in
Table 24-10 . Filtering can be controlled independently by engine, but all input
digital filters in the same engine have same clock prescaling. For more details see Section 24.5.5.6.5,
Filter Clock Prescaler .
Note: A new value written to FPSCK only becomes effective when the filter prescaler finishes the current
count.
Table 24-9. ETPU_ECR field description
Field Description
Table 24-10. Filter prescaler clock control
Filter control
Sample on system
clock divided by:
000 2
001 4
010 8
011 16
100 32
101 64
110 128
111 256