NXP Semiconductors MPC5644A, Reference Manual, Page: 1262 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1262 Freescale Semiconductor
30.8.2.2 DSPI Hardware Configuration Register (DSPI_HCR)
DSPI Hardware Configuration Register provides particular implementation details about the DSPImodule, i.e. number of Receive
and Transmit FIFO entries, number of CTAR registers and if DSI featuresare implemented in the module or not. It is read only
register.
18
DIS_TXF
Disable Transmit FIFO
When the TX FIFO is disabled, the transmit part of the DSPI operates as a simplified double-buffered
SPI. See
Section 30.9.2.3, FIFO disable operation , for details.
0 TX FIFO is enabled
1 TX FIFO is disabled
19
DIS_RXF
Disable Receive FIFO
When the RX FIFO is disabled, the receive part of the DSPI operates as a simplified double-buffered
SPI. See
Section 30.9.2.3, FIFO disable operation , for details.
0 RX FIFO is enabled
1 RX FIFO is disabled
20
CLR_TXF
Clear TX FIFO
CLR_TXF is used to flush the TX FIFO. Writing a ‘1’ to CLR_TXF clears the TX FIFO Counter. The
CLR_TXF bit is always read as zero.
0 Do not clear the TX FIFO Counter
1 Clear the TX FIFO Counter
21
CLR_RXF
Clear RX FIFO
CLR_RXF is used to flush the RX FIFO. Writing a ‘1’ to CLR_RXF clears the RX Counter. The
CLR_RXF bit is always read as zero.
0 Do not clear the RX FIFO Counter
1 Clear the RX FIFO Counter
22–23
SMPL_PT
Sample Point
SMPL_PT field controls when the DSPI master samples SIN in Modified Transfer Format.
Figure 30-40 shows where the master can sample the SIN pin.
00 DSPI samples SIN at driving SCK edge.
01 DSPI samples SIN one system clock after driving SCK edge
10 DSPI samples SIN two system clocks after driving SCK edge
11 Reserved
24–29 Reserved, should be cleared.
30
PES
Parity Error Stop
PES bit controls SPI operation when a parity error detected in received SPI frame.
0 SPI frames transmission continue.
1 SPI frames transmission stop.
31
HALT
Halt
The HALT bit starts and stops DSPI transfers. See
Section 30.9.1, Start and stop of DSPI transfers ,
for details on the operation of this bit.
0 Start transfers
1 Stop transfers
Table 30-4. DSPI_MCR field description (continued)
Field Description