NXP Semiconductors MPC5644A, Reference Manual, Page: 902 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
902 Freescale Semiconductor
Figure 24-57. Angle Ticks Generation
24.5.7.4.2 Generating the angle ticks
The integer part of TRR is preloaded to a prescaler, which counts down at input clock rate equals to the
TCR1 clock rate (TCR1CS = 0) or TCR1 clock rate divided by 2 (TCR1CS = 1) (see
Figure 24-56 ). When
the down counter reaches zero, it generates an angle tick pulse to the Angle Counter Logic and a Load
pulse to the Fraction Accumulator. It is then preloaded with most updated TRR integer part. Due to the
Load pulse, the 9-bit fraction is accumulated in a 9-bit Fraction Accumulator. If a fraction overflow
condition occurs (the 9-bit adder asserts carry out), the accumulator saves the lower 9 bits of the addition
result, which is the remaining fractional part. The carry out bit indicates an accumulated integer “one”
which means that the angle tick is early by one input clock. It halts the prescaler operation for one input
clock to compensate the accumulated error generated by the integer prescaler. As a result, the average
angle tick period takes into account both the integer and the fraction parts. The accuracy depends on the
bit count of the fraction. Using 9-bit fraction part while the width of the field TICKS in register TPR is 10
bits provides accuracy of two LSB on a full scale (TICKS = 1023) or one LSB on lower scale
(TICKS<=511).
When the Tick Prescaler gets High Rate mode indication from the Angle Counter Logic, it generates angle
ticks at a rate of system clock divided by eight. In this case it does not generate Load pulses to the Fraction
Accumulator, ignores its “hold” input and preloads internally to a fixed period of eight system clocks.
When High Rate mode is entered, the prescaler is preloaded to a period of eight system clocks before its
first angle tick generation, ensuring separation of at least eight system clocks between the last Normal
mode angle tick and the first High Rate mode angle tick. The fraction accumulator resets when the tick
count advances to the next tooth, or when TRR is written by the microcode.
24.5.7.5 Count control and high rate logic
The Count Control and High Rate Logic controls TCR2 operation in Angle Mode, using the angle ticks
generated by the Angle Tick Generator. Count Control logic is responsible for advancing, holding and
resetting the TCR2 and Tooth Tick Counter in the proper timing, such that the TCR2 time base will reflect
Tooth Signal
Angle Tick
P1 P2 P3
Acceptance window
from EAC channel
2 4 6 9 11 13 16 18 20 23
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
TCR1 Clocks
EAC Channel
Capture
TCR2
0 1 2
Glitch rejected
TCR1 = 1000 TCR1 = 1023 1046
3 6 9 2 5 8 1 4 7 0 3 6 9 2 5 8 1 4 7 0 3 6
0
Fraction
Accumulator
(modes m2_o_st/dt)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Tooth Tick Counter