NXP Semiconductors MPC5644A, Reference Manual, Page: 473 / 1735

System Integration Unit (SIU)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 473
16.6.15.86 Pad Configuration Register 133 (SIU_PCR133)
Figure 16-119. Pad Configuration Register (SIU_PCR133)
16.6.15.87 Pad Configuration Register 134 (SIU_PCR134)
Figure 16-120. Pad Configuration Register (SIU_PCR134)
S0x14A
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 0 PA OBE
1
1
The OBE bit must be set to one for both ETPUA and GPIO when configured as outputs.
IBE
2
2
The IBE bit must be set to one for both ETPUA and GPIO when configured as inputs. When configured as PCS, or
ETPUA or GPO outputs, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register.
0 0 ODE HYS SRC WPE WPS
3
3
The weak pull up/down selection at reset for the ETPU_A[19] pin is determined by the WKPCFG pin.
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 WKP
= Unimplemented or Reserved
Table 16-122. SIU_PCR133 PA values
Signal Name Module Description I/O
1,2
1
In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE
bits. Set IBE = 1 for input or OBE = 1 for output.
2
For I/O functions that change direction dynamically, such as the external data bus, switching between input and
output is handled internally and the IBE and OBE bits are ignored.
PA value
Primary ETPU_A[19] eTPU eTPU channel I/O 0b001
ALT1 DSPI_D_PCS[4] DSPI Chip select O 0b010
ALT2 RCH5_A Reaction Reaction channel O 0b100
GPIO GPIO[133] SIU GPIO I/O 0b000
S0x14C
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 PA OBE
1
1
When configured as IRQ, the OBE bit has no effect. The OBE bit must be set to one for both ETPU_A[20] and
GPIO[134] when configured as outputs.
IBE
2
2
When configured as FR_A_TX, IRQ or GPO, the IBE bit may be set to one to reflect the pin state in the
corresponding GPDI register. Setting the IBE bit to zero reduces power consumption. The IBE bit must be set to
one for both ETPU_A[20] and GPIO[134] when configured as inputs.
0 0 ODE HYS SRC WPE WPS
3
3
The weak pull up/down selection at reset for the ETPU_A[20] pin is determined by the WKPCFG pin.
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 WKP
= Unimplemented or Reserved