NXP Semiconductors MPC5644A, Reference Manual, Page: 273 / 1735

Memory Protection Unit (MPU)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 273
4. Typically, references to the MPU’s programming model would be restricted to supervisor mode
accesses from a specific processor(s), so a region descriptor would be specifically allocated for this
purpose with attempted accesses from other masters or while in user mode terminated with an error.
5. When the MPU detects an access error, the current XBAR bus cycle is terminated with an error
response and information on the faulting reference captured in the MPU_EAR n and MPU_EDR n
registers. The error-terminated XBAR bus cycle typically initiates some type of error response in
the originating bus master. For example, a processor core may respond with a bus error exception,
while a data movement bus master may respond with an error interrupt. In any event, the processor
can retrieve the captured error address and detail information simply be reading the
MPU_E{A,D}R
n registers. Information on which error registers contain captured fault data is
signaled by MPU_CESR[SPERR].
6. Finally, consider the use of overlapping region descriptors. Application of overlapping regions can
reduce the number of descriptors required for a given set of access controls. In the overlapping
memory space, the protection rights of the corresponding region descriptors are logically summed
together (the boolean OR operator). In the following example of a dual-core system, there are four
bus masters: the two processors (CP0, CP1) and two DMA engines (eDMA, a traditional data
movement engine transferring data between RAM and peripherals, and FlexRay, a second engine
transferring data to/from the RAM only). Consider the region descriptor assignments shown in
Table 13-11 :
In this example, there are eight descriptors used to span nine regions in the three main spaces of
the system memory map (flash, RAM, and IPS peripheral space). Each region indicates the specific
permissions for each of the four bus masters and this definition provides an appropriate set of
shared, private and executable memory spaces.
Of particular interest are the two overlapping spaces: region descriptors 2 and 3, and 3 and 4.
The space defined by RGD2 with no overlap is a private data and stack area that provides
read/write access to CP0 only. The overlapping space between RGD2 and RGD3 defines a shared
data space for passing data from CP0 to CP1 and the access controls are defined by the logical OR
of the two region descriptors. Thus, CP0 has (r w – | r – –) = (r w –) permissions, while CP1 has
Table 13-11. Overlapping region descriptor example
Region description RGDn CP0 CP1 eDMA FlexRay
Memory
map space
CP0 Code 0 r w x r – – – – – –
Flash
CP1 Code 1 r – – r w x – – – –
CP0 Data & Stack 2 r w – – – – – – – –
RAM
CP0 –> CP1 Shared Data
3
r – – r – – – – – –
CP1 –> CP0 Shared Data
CP0 Data & Stack 4 – – – r w – – – ––
Shared DMA Data 5 r w – r w – r w r w
MPU 6 r w – r w – – – – –
IPS
Peripherals 7 r w – r w – r w – –