NXP Semiconductors MPC5644A, Reference Manual, Page: 1537 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1537
Common configuration data
The set of common configuration data for individual message buffers is located in the following registers.
• Message Buffer Data Size Register (FR_MBDSR)
The MBSEG2DS and MBSEG1DS fields define the minimum length of the message buffer data
field with respect to the message buffer segment.
• Message Buffer Segment Size and Utilization Register (FR_MBSSUTR)
The LAST_MB_SEG1 and LAST_MB_UTIL fields define the segmentation of the individual
message buffers and the number of individual message buffers that are used. For more details, see
Section 33.6.3.1.1, Individual message buffer segments ”
Specific configuration data
The set of message buffer specific configuration data for individual message buffers is located in the
following registers.
• Message Buffer Configuration, Control, Status Registers (FR_MBCCSRn)
The MCM, MBT, MTD bits configure the message buffer type.
• Message Buffer Cycle Counter Filter Registers (FR_MBCCFRn)
The MTM, CHA, CHB bits configure the transmission mode and the channel assignment. The
CCFE, CCFMSK, and CCFVAL bits and fields configure the cycle counter filter.
• Message Buffer Frame ID Registers (FR_MBFIDRn)
For a transmit message buffer, the FID field is used to determine the slot in which the message in
this message buffer will be transmitted.
• Message Buffer Index Registers (FR_MBIDXRn)
This MBIDX field provides the index of the message buffer header field of the physical message
buffer that is currently associated with this message buffer.
33.6.3.5 Individual message buffer control data
During normal operation, each individual message buffer can be controlled by the control and trigger bits
CMT, LCKT, EDT, and MBIE in the
Message Buffer Configuration, Control, Status Registers
(FR_MBCCSRn) .
33.6.3.6 Receive shadow buffer configuration data
Before frame reception into the individual message buffers can be performed, the receive shadow buffers
must be configured. The configuration data are provided by the
Receive Shadow Buffer Index Register
(FR_RSBIR) . For each receive shadow buffer, the application provides the message buffer header index.
When the protocol is in the POC:normal active or POC:normal passive state, the receive shadow buffers
are under full CC control.
33.6.3.7 Receive FIFO control and configuration data
This section describes the configuration and control data for the two receive FIFOs.