NXP Semiconductors MPC5644A, Reference Manual, Page: 572 / 1735

Frequency-modulated phase locked loop (FMPLL)
MPC5644A Microcontroller Reference Manual, Rev. 6
572 Freescale Semiconductor
17.4.2.5 Synthesizer FM Modulation Register (SYNFMMR)
This register controls the frequency modulation (FM) features of the FMPLL. FM is not backwards
compatible with previous devices. Therefore, this register must be used in enhanced mode. It can only be
programmed when the FMPLL is locked. Writing to this register while the FMPLL is unlocked has no
effect. Furthermore, when the PLL loses lock, frequency modulation is disabled and the
FMPLL_SYNFMMR is reset.
9
LOLRE
Loss-of-lock reset enable
The LOLRE bit determines whether system reset is asserted or not upon a loss-of-lock indication. When
operating in normal mode, the FMPLL must be locked before setting the LOLRE bit, otherwise reset is
immediately asserted. Note that once reset is asserted, the operating mode is switched to bypass mode,
and once in bypass, a loss-of-lock condition does not generate reset, regardless of the value of the
LOLRE bit. See
Section 17.5.3, Lock detection .
0 Ignore loss-of-lock. Reset not asserted.
1 Assert reset on loss-of-lock when operating in normal mode.
10
LOCRE
Loss-of-clock reset enable
The LOCRE bit determines whether system reset is asserted or not upon a loss-of-clock condition when
LOCEN = 1. LOCRE has no effect when LOCEN = 0. If the LOCF bit in the SYNSR indicates a
loss-of-clock condition, setting the LOCRE bit causes immediate reset. In bypass mode with crystal
reference, reset will occur if the reference clock fails, even if LOCRE = 0 or even if LOCEN = 0. The
LOCRE bit has no effect in bypass mode with external reference. In this mode, the reference clock is not
monitored at all. See
Section 17.5.4.2, Loss-of-clock reset .
0 Ignore loss-of-clock. Reset not asserted.
1 Assert reset on loss-of-clock.
11
LOLIRQ
Loss-of-lock interrupt request
The LOLIRQ bit enables a loss-of-lock interrupt request when the LOLF flag is set. If either LOLF or
LOLIRQ is negated, the interrupt request is negated. When operating in normal mode, the FMPLL must
be locked before setting the LOLIRQ bit, otherwise an interrupt is immediately asserted. The interrupt
request only happens in normal mode, therefore the LOLIRQ bit has no effect in bypass mode. See
Section 17.5.3, Lock detection .
0 Ignore loss-of-lock. Interrupt not requested.
1 Enable interrupt request upon loss-of-lock.
12
LOCIRQ
Loss-of-clock interrupt request
The LOCIRQ bit enables a loss-of-clock interrupt request when the LOCF flag is set. If either LOCF or
LOCIRQ is negated, the interrupt request is negated. If loss-of-clock is detected while in bypass mode, a
system reset is generated. Therefore, LOCIRQ has no effect in bypass mode. See
Section 17.5.4.3,
Loss-of-clock interrupt request .
0 Ignore loss-of-clock. Interrupt not requested.
1 Enable interrupt request upon loss-of-clock.
13–29 Reserved, should be cleared.
30–31
ERFD Enhanced reduced frequency divider
This 2-bit field controls a divider at the output of the FMPLL. The value specified by the ERFD bits
establishes the division factor applied to the FMPLL frequency.
00 Divide by 2
01 Divide by 4
10 Divide by 8
11 Divide by 16
Table 17-9. ESYNCR2 field descriptions (continued)
Field Description