NXP Semiconductors MPC5644A, Reference Manual, Page: 1429 / 1735

FlexCAN Module
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1429
received frames sequentially, in the order they were received, by repeatedly accessing a Message Buffer
structure at the beginning of the memory.
The FIFO can store up to 6 frames pending service by the CPU. An interrupt is sent to the CPU when new
frames are available in the FIFO. Upon receiving the interrupt, the CPU must read the frame (accessing a
message buffer in the 0x80 address) and then clear the interrupt. The act of clearing the interrupt triggers
the FIFO engine to replace the message buffer in 0x80 with the next frame in the queue, and then issue
another interrupt to the CPU. If the FIFO is full and more frames continue to be received, an OVERFLOW
interrupt is issued to the CPU and subsequent frames are not accepted until the CPU creates space in the
FIFO by reading one or more frames. A warning interrupt is also generated when 5 frames are accumulated
in the FIFO.
A powerful filtering scheme is provided to accept only frames intended for the target application, thus
reducing the interrupt servicing work load. The filtering criteria is specified by programming a table of 8
32-bit registers that can be configured to one of the following formats (see also
Section 32.4.4, Rx FIFO
structure ):
• Format A: 8 extended or standard IDs (including IDE and RTR)
• Format B: 16 standard IDs or 16 extended 14-bit ID slices (including IDE and RTR)
• Format C: 32 standard or extended 8-bit ID slices
NOTE
A chosen format is applied to all 8 registers of the filter table. It is not
possible to mix formats within the table.
The eight elements of the filter table are individually affected by the first eight Individual Mask Registers
(RXIMR0 – RXIMR7), allowing very powerful filtering criteria to be defined. The rest of the RXIMR,
starting from RXIM8, continue to affect the regular message buffers, starting from MB8. If the MBFEN
bit is negated (or if the RXIMR are not available for the particular MCU), then the FIFO filter table is
affected by the legacy mask registers as follows: element 6 is affected by RX14MASK, element 7 is
affected by RX15MASK and the other elements (0 to 5) are affected by RXGMASK.
32.5.7.1 Precautions when using Global Mask and Individual Mask registers
Table 32-18. Recommended FEN and BCC settings
Case
MCR[FEN]
RxFIFO
MCR[BCC]
Rx Individual Mask
Notes
Case 1 FEN = 0 BCC = 0 RXGMASK, RX14MASK, and RX15MASK can safely be used.
This allows backwards compatibility to older devices (e.g.,
devices without the individual masks feature). In this case,
individual masks are not used.
Case 2 FEN = 1 BCC = 0 1st alternative:
Do not use RXGMASK, RX14MASK, and RX15MASK in this
case, leave the masks in their reset state.