NXP Semiconductors MPC5644A, Reference Manual, Page: 1545 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1545
33.6.5.2.2 Data field offset description
Data field offset content
For a detailed description of the Data Field Offset, see Section 33.6.2.1.2, Data field offset ”.
Data field offset access
The application shall program the Data Field Offset when configuring the message buffers either in the
POC:config state or when the message buffer is disabled.
33.6.5.2.3 Slot status description
The slot status is a read-only structure for the application and a write-only structure for the CC. The
meaning and content of the slot status in the message buffer header field depends on the message buffer
type.
Receive message buffer and receive FIFO slot status description
This section describes the slot status structure for the individual receive message buffers and receive
FIFOs. The content of the slot status structure for receive message buffers depends on the message buffer
type and on the channel assignment for individual receive message buffers as given by
Table 33-97 .
SYF Sync Frame Indicator — This bit is not used, the value of the Sync Frame Indicator is generated
internally according to FlexRay Communications System Protocol Specification, Version 2.1 Rev A.
SUF Startup Frame Indicator — This bit is not used, the value of the Startup Frame Indicator is generated
internally according to
FlexRay Communications System Protocol Specification, Version 2.1 Rev A.
FID Frame ID — This field is checked as described in Frame header checks .
CYCCNT Cycle Count — This field is not used, the value of the transmitted Cycle Count field is taken from the
internal communication cycle counter.
PLDLEN Payload Length — This field is checked and used as described in Frame header checks .
HDCRC Header CRC — This field provides the value of the Header CRC field for the frame transmitted from
the message buffer.
Table 33-97. Receive message buffer slot status content
Receive message buffer type Slot status content
Individual Receive Message Buffer assigned to both channels
FR_MBCCFRn[CHA] = 1 and FR_MBCCFRn[CHB] = 1
see Figure 33-122
Individual Receive Message Buffer assigned to channel A
FR_MBCCFRn[CHA] = 1 and FR_MBCCFRn[CHB] = 0
see Figure 33-123
Individual Receive Message Buffer assigned to channel B
FR_MBCCFRn[CHA] = 0 and FR_MBCCFRn[CHB] = 1
see Figure 33-124
Table 33-96. Frame header field description (transmit message buffer)
Field Description