NXP Semiconductors MPC5644A, Reference Manual, Page: 1178 / 1735

Decimation Filter
MPC5644A Microcontroller Reference Manual, Rev. 6
1178 Freescale Semiconductor
26.4.2
Decimation filter register descriptions
All registers are 32-bit wide.
26.4.2.1 Decimation Filter Module Configuration Register (DECFILTER_MCR)
The Decimation Filter module configuration register provides configuration control bits for the
Decimation Filter internal logic.
NOTE
One must not modify this register contents when the status bit BSY is set,
except for fields FREN, FRZ and IDIS. To guarantee that BSY does not set
during the read-modify-write operation, it is advisable to set IDIS = 1 and
wait for BSY = 0 beforehand.
0x0E8 Decimation Filter Current Integration Value Register
(DECFILTER_CINTVAL) on page
26-1198
0x0EC Decimation Filter Current Integration Count Value
Register (DECFILTER_CINTCNT) on page
26-1199
0x0F0–0x1FF Reserved
1
The TAP register stores, on each filter node, the input sample data and, for the IIR type, the filter
intermediary results.
Address: DECFILTE 0x000 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
MDIS
FREN
0
FRZ
0
CASCD[1:0] IDEN
ODEN
ERREN
0
FTYPE[1:0]
0
SCAL[1:0] W
SRES
Reset —
1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
IDIS SAT ISEL
MI
X
M
DEC_RATE[3:0] SDIE
DSEL
IBIE OBIE
EDME
TO
R
E
TMODE[1:0]
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
Reset value is defined by the MDIS_DEFAULT parameter value.
Figure 26-2. Decimation Filter Module Configuration Register (DECFILTER_MCR)
Table 26-3. Decimation filter device memory map (continued)
Offset from DECFILTER_
BASE
0xFFF8_8000 (Filter A)
0xFFF8_C000 (Filter B)
Register Location