NXP Semiconductors MPC5644A, Reference Manual, Page: 649 / 1735

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 649
22.4.2 Global registers
All global control registers are 32-bit wide but some do not use the most significant 8 bits because the
MPC5644A has 24 channels and 24-bit counters.
22.4.2.1 eMIOS200 Module Configuration Register (EMIOS_MCR)
The EMIOS_MCR contains global control bits for the eMIOS200 module.
1
The alternate address register provides and alternate read-only address to access A2 channel
register in GPIO modes. If EMIOS_CADR[
n ] is used with EMIOS_ALTA[ n ], both A1 and A2 registers
can be accessed in these modes.
Address: EMIOS_BASE (0xC3FA_0000) + 0x0000 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 MDIS FRZ GTBE ETB GPREN 0 0 0 0 0 0 SRV[0:3]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R GPRE[0:7] 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 22-2. eMIOS200 Module Configuration Register (EMIOS_MCR)
Table 22-3. EMIOS_MCR field description
Field Description
MDIS Module Disable
Puts the eMIOS200 in low power mode. The MDIS bit is used to stop the clock to the module, except
access to the EMIOS_MCR, EMIOS_OUDR and EMIOS_UCDIS registers.
0 Clock is running
1 Enter low power mode
FRZ Freeze
Enables the eMIOS200 to freeze the channel registers when Debug Mode is requested at the MCU
level. Each channel should have the FREN bit set in its EMIOS_CCR[n] register order to enter the
freeze state. While in Freeze state, the eMIOS200 continues to operate to allow the MCU access
to the channel registers. The channel remains frozen until the FRZ bit is written to zero, the MCU
exits Debug mode or the channel’s FREN bit is cleared.
0 Exit freeze state
1 Stops channels operation when in Debug mode and the FREN bit is set in the EMIOS_CCR[n]
register