NXP Semiconductors MPC5644A, Reference Manual, Page: 159 / 1735

Enhanced Direct Memory Access Controller (eDMA)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 159
8.3.2.11 eDMA Set START Bit Register (EDMA_SSBR)
The EDMA_SSBR provides a memory-mapped mechanism to set the START bit in the TCD of the given
channel. The data value on a register write causes the START bit in the corresponding transfer control
descriptor to be set. Setting bit 1 (SSB[0]) provides a global set function, forcing all START bits to be set.
Reads of this register return all zeroes.
If bit 0 is set, the SSB command is ignored. This allows multiple byte registers to be written as a 32-bit
word. Reads of this register return all zeroes.
8.3.2.12 eDMA Clear DONE Status Bit Register (EDMA_CDSBR)
The EDMA_CDSBR provides a memory-mapped mechanism to clear the DONE bit in the TCD of the
given channel. The data value on a register write causes the DONE bit in the corresponding transfer control
descriptor to be cleared. Setting bit 1 (CDSB[0]) provides a global clear function, forcing all DONE bits
to be cleared.
If bit 0 is set, the CDSB command is ignored. This allows multiple byte registers to be written as a 32-bit
word. Reads of this register return all zeroes.
Offset: EDM 0x001E Access: User write-only
0 1 2 3 4 5 6 7
R
W NOP SSB[0:6]
Reset 0 0 0 0 0 0 0 0
Figure 8-14. eDMA Set START Bit Register (EDMA_SSBR)
Table 8-13. EDMA_SSBR field descriptions
Field Description
NOP No operation
0 Normal operation
1 No operation, ignore bits 1–7.
SSB[0:6] Set START Bit (channel service request)
0–32 (64 for eDMA) Set the corresponding channel’s TCD START bit.
64–127
Set all TCD START bits.
Offset: EDM 0x001F Access: User write-only
0 1 2 3 4 5 6 7
R
W NOP CDSB[0:6]
Reset 0 0 0 0 0 0 0 0
Figure 8-15. eDMA Clear DONE Status Bit Register (EDMA_CDSBR)