NXP Semiconductors MPC5644A, Reference Manual, Page: 1448 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
1448 Freescale Semiconductor
33.4.1 Oscillator clocking
If the protocol engine is clocked by the internal crystal oscillator, an 40 MHz crystal or CMOS compatible
clock must be connected to the oscillator pins. The crystal or clock must fulfill the requirements given by
the
FlexRay Communications System Protocol Specification, Version 2.1 Rev A.
33.4.2 PLL clocking
If the protocol engine is clocked by the internal PLL, the frequency of the PE clock source is
system clock / 3. The system clock frequency has to be 120 MHz.
33.5 Memory map and register description
The CC occupies 1280 bytes of address space starting at the base address of the CC is defined by the
memory map of the MCU.
33.5.1 Memory map
The complete memory map of the CC is shown in Table 33-3 . The addresses presented here are the offsets
relative to the CC base address which is defined by the MCU address map.
Table 33-3. FlexRay memory map
Offset Register Access Location
Module Configuration and Control
0x0000 Module Version Register (FR_MVR) R on page
33-1456
0x0002 Module Configuration Register (FR_MCR) R/W on page
33-1457
0x0004 System Memory Base Address High Register (FR_SYMBADHR) R/W on page
33-1459
0x0006 System Memory Base Address Low Register (FR_SYMBADLR) R/W on page
33-1459
0x0008 Strobe Signal Control Register (FR_STBSCR) R/W on page
33-1460
0x000A Reserved R —
0x000C Message Buffer Data Size Register (FR_MBDSR) R/W on page
33-1461
0x000E Message Buffer Segment Size and Utilization Register (FR_MBSSUTR) R/W on page
33-1462
PE Access Registers
0x0010 PE DRAM Access Register (FR_PEDRAR) R/W on page
33-1462