NXP Semiconductors MPC5644A, Reference Manual, Page: 121 / 1735

Device Performance Optimization
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 121
priority master and grants it ownership of the slave port. All other masters requesting that slave port are
stalled until the higher priority master completes its transactions. By default, requesting masters are
granted access based on a fixed priority. A round-robin priority mode also is available.
The main goal of the XBAR is to increase overall system performance by allowing multiple masters to
communicate concurrently with multiple slaves. In order to maximize data throughput it is essential to
keep arbitration delays to a minimum. The configuration of the crossbar can have implications for the
performance of a system and particular care should be taken when assigning master priorities in a fixed
priority application. Further, by correctly parking saves on relevant masters the initial access times to the
slaves can be minimized by negating any initial arbitration penalties.
6.3.4.2 Recommended configuration
The specific settings for a given situation are application dependent and thus should be assessed by the
user. However, some general guidelines are available.
Optimal XBAR settings are application dependent, but in e200z4/7 (Harvard configuration) based devices
assigning the CPU data bus to have highest priority and parking the slave port associated with system
RAM on this master generally provides the best overall performance.
To reconfigure the XBAR as described on the MPC5644A, write the following registers:
1. XBAR_SGPCR2 = 0x0000_0001. This parks slave 2 (internal SRAM) on master port 1 (CPU data
bus).
2. Write XBAR_MPR0 = 0x5432_0001. This sets slave port 0 (Flash) to give the master port 1 (CPU
data bus) highest priority.
On the e200z4 based devices it may also be beneficial to assign the eDMA to have highest priority for the
Flash slave port depending upon the application.
More details of the XBAR register configuration can be found in Section 9.2, XBAR registers .
6.3.5 Cache
6.3.5.1 Description
The MPC5644A provides an 8 KB Instruction, 2-way or 4-way set-associative, Harvard cache design with
a 32-byte line size. The cache is disabled by default when reset is negated.
The cache improves system performance by providing low-latency instructions to the e200z4 instruction
pipelines, which decouples processor performance from system memory performance. There are several
stages to enabling the cache. Not only does the cache itself have to be invalidated then enabled, but
memory regions upon which it can operate must be configured in the MMU to permit cache access.
6.3.5.2 Recommended configuration
The exact usage of cache is application dependent but some general guidelines for using cache to improve
performance in a typical application are listed below:
• Enable instruction cache for all internal and external memories that code is being executed from.