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Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
1143
25.6.9
EQADC Synchronous Serial Interface (SSI) Sub-Block
Figure 25-85.
EQADC
Synchronous Serial Interface Block Diagram
The EQADC SSI protocol allows for a full duplex, synchronous, serial communication between the
EQADC and a single external device.
shows the different components inside the EQADC
SSI block. The EQADC SSI sub-block on the EQADC is always configured as a master. The EQADC SSI
has four associated port pins:
•
Free running Clock (FCK)
•
Serial Data Select (SDS)
•
Serial Data In (SDI)
•
Serial Data Out (SDO)
The FCK clock signal times the shifting and sampling of the two serial data signals and it is free running
between transmissions, allowing it to be used as the clock for the external device. The SDS signal will be
asserted to indicate the start of a transmission, and negated to indicate the end or the abort of a
transmission. SDI is the master serial data input and SDO the master serial data output.
The EQADC SSI sub-block is enabled by setting the ESSIE field in the
Section 25.5.2.1, EQADC Module
Configuration Register (EQADC_MCR)
. When enabled, the EQADC SSI can be optionally capable of
starting serial transmissions. When serial transmissions are disabled (ESSIE set to 0b10), no data will be
transmitted to the external device but FCK will be free-running. This operation mode permits the control
of the timing of the first serial transmission, and can be used to avoid the transmission of data to an unstable
external device, for example, a device that is not fully reset. This mode of operation is specially important
for the reset procedure of an external device that uses the FCK as its main clock.
Master
Slave In
Out
Pad
Interface
SDS
FCK
SDO
SDI
EQADC SSI Control Register
FCK
Clock
System
Transmit Shift Register
EQADC SSI Control Logic
Receive Shift Register
BR
CFIFO Data
RFIFO Data
EQADC FIFO
Control Unit
Control
MDT
Clock
Divide by: 2, 3, 4,
.. , 15, 16, 17
Baud Clock Generator
Slave Bus interface
Summary of Contents for MPC5644A
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Page 24: ...MPC5644A Microcontroller Reference Manual Rev 6 24 Freescale Semiconductor...
Page 26: ...MPC5644A Microcontroller Reference Manual Rev 6 26 Freescale Semiconductor...
Page 52: ...Introduction MPC5644A Microcontroller Reference Manual Rev 6 52 Freescale Semiconductor...
Page 56: ...Memory Map MPC5644A Microcontroller Reference Manual Rev 6 56 Freescale Semiconductor...
Page 1228: ...Decimation Filter MPC5644A Microcontroller Reference Manual Rev 6 1228 Freescale Semiconductor...
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