NXP Semiconductors MPC5644A, Reference Manual, Page: 272 / 1735

Memory Protection Unit (MPU)
MPC5644A Microcontroller Reference Manual, Rev. 6
272 Freescale Semiconductor
assignments. For an example of the use of overlapping region descriptors, see Section 13.7, Application
Information .
When the MPU causes a termination error to occur, the effect on the system depends on the bus master
requesting the access. If the error was caused by a core access, a machine check is taken. If the error was
caused by an eDMA access, an eDMA source or destination error occurs in the eDMA controller, which
can be enabled to provide an interrupt request through the INTC. If the error was caused by a FlexRay
access, a controller host interface (CHI) illegal system memory access error occurs in the FlexRay
controller, which can be enabled to provide an interrupt request to the INTC.
13.6 Initialization Information
The reset state of MPU_CESR[VLD] disables the entire module. While the MPU is disabled, all accesses
from all bus masters are allowed. This state also minimizes the power dissipation of the MPU. The power
dissipation of each access evaluation macro is minimized when the associated region descriptor is marked
as invalid or when MPU_CESR[VLD] = 0.
Typically the appropriate number of region descriptors (MPU_RGD n ) are loaded at system startup,
including the setting of the MPU_RGD n .Word3[VLD] bits, before MPU_CESR[VLD] is set, enabling the
module. This approach allows all the loaded region descriptors to be enabled simultaneously. Once the
MPU is enabled, if a memory reference does not hit in any region descriptor, the attempted access is
terminated with an error.
13.7 Application Information
In an application’s system, interfacing with the MPU can generally be classified into the following
activities:
1. Creation of a new memory region requires loading the appropriate region descriptor into an
available register location. When a new descriptor is loaded into a RGD n , it would typically be
performed using four 32-bit word writes. As discussed in Section 13.4.2.4.4, MPU Region
Descriptor n, Word 3 (MPU_RGDn.Word3) , the hardware assists in the maintenance of the valid
bit, so if this approach is followed, there are no coherency issues associated with the multi-cycle
descriptor writes. Deletion/removal of an existing memory region is performed by clearing
MPU_RGD
n .Word3[VLD].
2. If only the access rights for an existing region descriptor need to change, a 32-bit write to the
alternate version of the access control word (MPU_RGDAAC n ) would typically be performed.
Writes to the region descriptor using this alternate access control location do not affect the valid
bit, so there are, by definition, no coherency issues involved with the update. The access rights
associated with the memory region switch instantaneously to the new value as the IPS write
completes.
3. If the region’s start and end addresses are to be changed, this would typically be performed by
writing a minimum of three words of the region descriptor: MPU_RGD n .Word{0,1,3}, where the
writes to Word0 and Word1 redefine the start and end addresses respectively and the write to
Word3 re-enables the region descriptor valid bit. In many situations, all four words of the region
descriptor would be rewritten.