NXP Semiconductors MPC5644A, Reference Manual, Page: 1303 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1303
PCSCSK and CSSCK fields have no effect in TSB configuration.
30.9.5.3 After SCK delay (t
ASC
)
The After SCK Delay is the length of time between the last edge of SCK and the negation of PCS. See
Figure 30-38 and Figure 30-39 for illustrations of the After SCK delay. The PASC and ASC fields in the
DSPI_CTAR x registers select the After SCK Delay by the formula in the ASC field description.
Table 30-35 shows an example of how to compute the After SCK delay.
PCASC and ASC fields have no effect in TSB configuration.
30.9.5.4 Delay after transfer (t
DT
)
The Delay after Transfer is the minimum time between negation of the PCS signal for a frame and the
assertion of the PCS signal for the next frame. See
Figure 30-38 for an illustration of the Delay after
Transfer. The PDT and DT fields in the DSPI_CTAR x registers select the Delay after Transfer by the
formula in the DT field description. Table 30-36 shows an example of how to compute the Delay after
Transfer.
When in non-continuous clock mode the t
DT
delay is configured according Equation 30-3 . When in
continuous clock mode and TSB is not enabled the delay is fixed at 1 SCK period.
In TSB mode the Delay after Transfer is equal to a number formed by concatenation of PDT and DT fields
plus 1 of the SCK clock periods. See detailed information in
Section 30.9.8, Timed serial bus (TSB) ”.
30.9.5.5 Peripheral chip select strobe enable (PCSS)
The PCSS signal provides a delay to allow the PCS signals to settle after a transition occurs thereby
avoiding glitches. When the DSPI is in master mode and PCSSE bit is set in the DSPI_MCR, PCSS
provides a signal for an external demultiplexer to decode the DSPI_x_PCS[0] – PCS[4] signals into as
many as 128 glitch-free PCS signals.
Figure 30-37 shows the timing of the PCSS signal relative to PCS
signals.
Table 30-35. After SCK delay computation example
f
sys
PASC Prescaler ASC Scaler After SCK delay
100 MHz 0b01 3 0b0100 32 0.96 µs
Table 30-36. Delay after transfer computation example
f
sys
PDT Prescaler DT Scaler Delay after transfer
100 MHz 0b01 3 0b1110 32768 0.98 ms