NXP Semiconductors MPC5644A, Reference Manual, Page: 990 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
990 Freescale Semiconductor
Figure 24-76. Execution, Timebase and Channel T2/T4 Timing
The sequential occurrence of the four T states (T1 – T4) constitutes a microcycle. Only T2 and T4 are
taken as reference for timings, either internal or external. T2 and T4 have the timing of the positive system
clock pulses, and are used in most of the eTPU logic in an edge-triggered design style.
Two additional T states are derived from the system clocks: T2 and T4. T2 occurs when the eTPU loses
SPRAM arbitration to a bus master. T4 occurs in halt state (due to a breakpoint or device debug request
assertion, for instance), or in stall state (due to an NDEDI queue full); see
Section 24.5.10.2, Development
support features , for more details.
T2 and T4 states are defined as microcycle timing states (not to be confounded with logic states) of one
system clock in which the T clocks continue to run, but the control signals associated with the clocks are
unaffected. That is, no operation occurs during these states. Both T2 and T4 states occur in multiples of
two system clocks to keep the microengine synchronized with the free running channels, which are
unaffected and keep on working as in T2 and T4.
Thus, the eTPU has two types of timing states:
TCR1/2*
T2 T4 T2 T4 T2 T4
1 microcycle 1 microcycle 1 microcycle
t
n-1
t
n
t
n-3
MRLA/B
TDLA/B
CAP1/2
Pin Action
due Match
uInstr
uInst
n
uInst
n+1
uInst = Set Pin
Pin Action
due uInstr
Note: * TCR clock/prescaler selection = 1 x system clock
Updated Pin Value
uInstr
uInst
n
Pre-fetch
uInst
n+1
uInst
n+2
Execution
System
Clock
T4
(match on t
n
)
t
n-2
t
n+1
t
n+2
t
n+3
t
n+4
t
n
Updated Pin Value