NXP Semiconductors MPC5644A, Reference Manual, Page: 171 / 1735

Enhanced Direct Memory Access Controller (eDMA)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 171
249 /
0x1C [25]
ACTIVE Channel active
This flag signals the channel is currently in execution. It is set when channel
service begins, and is cleared by the DMA engine as the inner minor loop
completes or if any error condition is detected.
250 /
0x1C [26]
MAJOR.E_LINK Enable channel-to-channel linking on major loop completion
As the channel completes the outer major loop, this flag enables the linking to
another channel, defined by MAJOR.LINKCH[0:5]. The link target channel
initiates a channel service request via an internal mechanism that sets bit
EDMA_TCD[START] of the specified channel.
Note: To support the dynamic linking coherency model, this field is forced to
zero when written to while the bit EDMA_TCD[DONE] is set.
0 The channel-to-channel linking is disabled.
1 The channel-to-channel linking is enabled.
251 /
0x1C [27]
E_SG Enable scatter-gather processing
As the channel completes the outer major loop, this flag enables scatter-gather
processing in the current channel. If enabled, the DMA engine uses
DLAST_SGA as a memory pointer to a 0-modulo-32 address containing a
32-byte data structure which is loaded as the transfer control descriptor into the
local memory.
Note: To support the dynamic scatter-gather coherency model, this field is
forced to zero when written to while the bit EDMA_TCD[DONE] is set.
0 The current channel’s TCD is normal format.
1 The current channel’s TCD specifies a scatter gather format. The
DLAST_SGA field provides a memory pointer to the next TCD to be loaded
into this channel after the outer major loop completes its execution.
252 /
0x1C [28]
D_REQ Disable hardware request
If this flag is set, the eDMA hardware automatically clears the corresponding
EDMA_ERQH or EDMA_ERQL bit when the current major iteration count
reaches zero.
0 The channel’s EDMA_ERQH or EDMA_ERQL bit is not affected.
1 The channel’s EDMA_ERQH or EDMA_ERQL bit is cleared when the outer
major loop is complete.
253 /
0x1C [29]
INT_HALF Enable an interrupt when major counter is half complete
If this flag is set, the channel generates an interrupt request by setting the
appropriate bit in the EDMA_ERQH or EDMA_ERQL when the current major
iteration count reaches the halfway point. Specifically, the comparison
performed by the eDMA engine is (CITER == (BITER >> 1)). This halfway point
interrupt request is provided to support double-buffered (aka ping-pong)
schemes, or other types of data movement where the processor needs an early
indication of the transfer’s progress. CITER = BITER = 1 with INT_HALF
enabled will generate an interrupt as it satisfies the equation (CITER == (BITER
>> 1)) after a single activation.
0 The half-point interrupt is disabled.
1 The half-point interrupt is enabled.
Table 8-20. TCDn field descriptions (continued)
Bits /
Word offset
[n:n]
Name Description