NXP Semiconductors MPC5644A, Reference Manual, Page: 698 / 1735

Reaction Module (REACM)
MPC5644A Microcontroller Reference Manual, Rev. 6
698 Freescale Semiconductor
Figure 23-4. REACM module configuration register (REACM_MCR)
Address: REACM_BASE (0xC3FC_7000) + 0x0000 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
MDIS
FRZ
0
FREN
TPREN
HPREN
GI
EN
OVREN
0 0 0 0 0 0 0
W
OVRC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 23-4. REACM_MCR field descriptions
Field Description
0
OVRC
Overrun Detection Flag Clear
The OVRC clears the OVR flag if write 0x1. This bit reads always as 0x0. If a set event occurs at the
same time a flag clear is done, the set event has precedence over the clear thus the flag remains set.
0 No action
1 Clears OVR bit
1
MDIS
Module Disable
The MDIS bit puts the Reaction Module in low power mode. Communication through the slave-bus
Interface is ignored in this mode except writes to the REACM_MCR which are allowed, except for the
FRZ and FREN bits. The global debug signal state is not changed internally while in low power mode.
0 Normal Mode
1 Low Power Mode
2
FRZ
Freeze Control
The FRZ bit controls the state of the Reaction Module regarding debug operation. If FREN bit is asserted
and FRZ bit is also asserted the module enters debug mode. In this mode all time bases are halted and
the channels outputs are controlled solely by software. See
Section 23.1.2.4, Debug mode . This bit
cannot be written if MDIS bit is asserted or when the Reaction Module is in stopped by a device stop
request.
0 Normal Mode
1 Debug Mode
3 Reserved, should be cleared.
4
FREN
Freeze Enable
The FREN bit enables the Reaction Module to enter debug mode. The debug mode is controlled either
by the FRZ bit or by a global debug signal. This bit cannot be written if MDIS bit is asserted or when the
Reaction Module is in stopped by a device stop request.
0 Debug Mode disabled
1 Debug Mode enable
5
TPREN
Timer Prescaler Enable
The TPREN bit enables the Shared Timer Prescaler in the Reaction Module.
0 Prescaler Disabled
1 Prescaler Enabled