NXP Semiconductors MPC5644A, Reference Manual, Page: 551 / 1735

System Integration Unit (SIU)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 551
16.6.34 Core MMU PID Control Register (SIU_EMPCR0)
The SIU_EMPCR0 register is part of a mechanism that provides the capability of real-time remapping of
MMU entries by software or an external tool. This capability is intended for use in calibration activities
requiring real-time switching between calibration data tables.
The SIU_EMPCR0 register works in conjunction with the Nexus module to enable an external calibration
tool to modify the logical-to-physical address mapping of the calibration bus by replacing bits 6:7 of the
MMU’s PID (process id) register with values specified in SIU_EMPCR0 register fields. This remapping
does not interrupt normal application code execution.
In addition, the register provides a synchronization mechanism that enables the mapping to change when
a specified instruction address is reached or a specified load/store address is accessed. Synchronization is
implemented using Watchpoint Event 2 output in the processor core.
The mechanism is detailed in Figure 16-219 and Table 16-220 .
See application note AN4030 for more detail.
22
SPIBACK
DSPI B stop acknowledge
When asserted, indicates that a stop acknowledge was received from the DSPI B.
1: Stop mode request
0: Normal operation
23:28 Reserved
29
eSCI C stop acknowledge
When asserted, indicates that a stop acknowledge was received from the eSCI C module.
1: Stop mode request
0: Normal operation
30
SCIBACK
eSCI B stop acknowledge
When asserted, indicates that a stop acknowledge was received from the eSCI B module.
1: Stop mode request
0: Normal operation
31
SCIAACK
eSCI A stop acknowledge
When asserted, indicates that a stop acknowledge was received from the eSCI A module.
1: Stop mode request
0: Normal operation
Table 16-219. SIU_HLTACK field description (continued)
Field Description