NXP Semiconductors MPC5644A, Reference Manual, Page: 661 / 1735

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 661
• A programmable clock prescaler
• Two double buffered data registers A and B that allow up to two input capture and/or output
compare events to occur before software intervention is needed.
• Two comparators (equal only) A and B, which compares the selected counter bus with the value in
the data registers
• Internal counter, which can be used as a local time base or to count input events
• Programmable input filter, which ensures that only valid pin transitions are received by channel
• Programmable input edge detector, which detects the rising, falling or either edges
• An output flip-flop, which holds the logic level to be applied to the output pin
• eMIOS200 Status and Control register
• An Output Disable Input selector, which selects the Output Disable Input signal that will be used
as output disable
Figure 22-12. Unified Channel block diagram
Channel Controller
Clock
Prescaler
Programmable
Filter
Channel Data Path
Comparator A
Comparator B
uc_cnt_rd_data[ n ]
uc_cnt_rd_data[ n ]
Counter Bus[0]
Counter Bus[1]
Match Logic
Mode Logic
Counter Bus
Unified Channel
Control Signals