External Bus Interface (EBI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
299
14.5.1.11 Slower-Speed Clock Modes
For memories that cannot run with a full-speed external bus, the EBI supports slower-speed clock modes.
Refer to
Section 14.2.3.4, Slower-speed modes
for more details on this feature. The timing diagrams for
slower-speed modes are identical to those for full-speed mode, except that the frequency of CLKOUT is
reduced.
14.5.1.12 Stop and Module Disable Modes for Power Savings
Section 14.2.3, Modes of operation
for a description of the power saving modes.
14.5.1.13 Optional Automatic CLKOUT Gating
The EBI has the ability to hold the external CLKOUT pin high when the EBI’s internal master state
machine is idle and no requests are pending. The EBI outputs a signal to the pads logic in the MCU to
disable CLKOUT. This feature is disabled out of reset, and can be enabled or disabled by the ACGE bit in
the EBI_MCR.
NOTE
This feature must be disabled for multi-master systems. In those cases, one
master is getting its clock source from the other master and needs it to stay
valid continuously.
Table 14-11. Write/Byte Enable Signals Function
1
1
This table applies to aligned internal master transfers only. In the case of a misaligned
internal master transfer that is split into multiple aligned external transfers, not all of the
write enables X’d in the table will necessarily assert. See
.
Transfer
Size
Address
32-Bit Port Size
16-Bit Port Size
2
2
Also applies when DBM=1 for 16-bit data bus mode.
A30
A31
WE0/
BE0
WE1/
BE1
WE2/
BE2
WE3/
BE3
WE0/
BE0
WE1/
BE1
WE2/
BE2
WE3/
BE3
Byte
0
0
X
X
0
1
X
X
1
0
X
X
1
1
X
X
16-bit
0
0
X
X
X
X
1
0
X
X
X
X
32-bit
0
0
X
X
X
X
X
3
3
This case consists of two 16-bit external transactions, but for both transactions the
WE[0:1]/BE[0:1] signals are the only WE/BE signals affected.
Burst
0
0
X
X
X
X
X
X
Summary of Contents for MPC5644A
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