NXP Semiconductors MPC5644A, Reference Manual, Page: 852 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
852 Freescale Semiconductor
Channel Selection Register – CHAN
CHAN is the register that holds the number of the channel that qualifies the context of most Channel
Registers, including Pin Control and ER accesses, and is common to all channels in a same engine.
When a thread starts to be executed, the contents of CHAN register is automatically updated on Time Slot
transition to the number of the channel to be serviced. Serviced channel is constant during channel
servicing, but the selected channel can be changed any time by microengine writing into CHAN register.
Some microinstructions are affected by the serviced channel instead of CHAN. These are:
• Conditional branch using LSR (see Section 24.5.8.1.6, LINK Register ) or Function Mode
( Section 24.4.7.2, ETPU_CxSCR – eTPU Channel x Status Control Register ).
• Negate channel flag LSR, Interrupt CPU and Data Transfer Request (see Section 24.5.9.3.10,
Channel interrupt and data transfer requests ).
When CHAN register is written, accesses are qualified by the new CHAN register value from the
instruction following CHAN assignment on, except CaptureA/B sampling into ERTA/B and Match
register writing from ERTA/B (see
Section 24.5.9.6.5, CHAN assignment, Read Match and ERWA/B ).
Writing CHAN (including with the same value, CHAN:= CHAN) updates ERTA and ERTB with the new
captured values, the branch logic with updated MRLA/B and TDLA/B flags.
Table 24-48 shows the commands, flags and registers selected by the CHAN register value
Table 24-47. General Channel registers microcode access
Register Access type
Sampled from
channel
Update to
channel
Microcode
fields
1
1
See Section 24.5.9, Microinstruction set .
Reset value
CHAN read/write n.a.
2
2
CHAN is common to all channels in the engine.
n.a.
2
T4ABS, T4BBS,
T2ABD
defaults to
serviced channel
at thread start
PDCM write only no immediate PDCM 1100
(sm_st)
UDCM write only no from ERTA by
microcode
CMW, ERWA parameter value
defined at
integration
SRI write only no immediate MTD 1
Flag1,Flag0 branch flag test,
write
no immediate BCC,FLC 0, 0
Table 24-48. CHAN-selected features
Feature used
Selected by
CHAN
Channel-relative SPRAM access YES
Branch using PSS, PRSS, PSTI and PSTO channel flags YES