NXP Semiconductors MPC5644A, Reference Manual, Page: 1421 / 1735

FlexCAN Module
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1421
Figure 32-17. Rx Individual Mask Registers (RXIMR0 – RXIMR63)
32.5 Functional description
32.5.1 Overview
The FlexCAN module is a CAN protocol engine with a very flexible mailbox system for transmitting and
receiving CAN frames. The mailbox system is composed by a set of up to 64 Message Buffers (MB) that
store configuration and control data, time stamp, message ID and data (see
Section 32.4.3, Message buffer
structure ). The memory corresponding to the first eight message buffers can be configured to support a
FIFO reception scheme with a powerful ID filtering mechanism, capable of checking incoming frames
against a table of IDs (up to eight extended IDs or sixteen standard IDs or thirty-two 8-bit ID slices), each
one with its own individual mask register. Simultaneous reception through FIFO and mailbox is supported.
For mailbox reception, a matching algorithm makes it possible to store received frames only into message
buffers that have the same ID programmed on its ID field. A masking scheme makes it possible to match
the ID programmed on the message buffer with a range of IDs on received CAN frames. For transmission,
an arbitration algorithm decides the prioritization of message buffers to be transmitted based on the
message ID (optionally augmented by three local priority bits) or the message buffer ordering.
Before proceeding with the functional description, an important concept must be explained. A Message
Buffer is said to be “active” at a given time if it can participate in the matching and arbitration algorithms
that are happening at that time. An Rx message buffer with a ‘0000’ code is inactive (refer to
Table 32-5 ).
Similarly, a Tx message buffer with a ‘1000’ or ‘1001’ code is also inactive (refer to Table 32-6 ). A
message buffer not programmed with ‘0000’, ‘1000’ or ‘1001’ will be temporarily deactivated (will not
participate in the current arbitration or matching run) when the CPU writes to the C/S field of that message
buffer (see
Section 32.5.6.2, Message buffer deactivation ).
Base + 0x0880–0x097F
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MI31 MI30 MI29 MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
MI15 MI14 MI13 MI12 MI11 MI10 MI9 MI8 MI7 MI6 MI5 MI4 MI3 MI2 MI1 MI0
Table 32-17. RXIMR0 – RXIMR63 Register field descriptions
Field Description
MI31–MI0 Mask Bits
For normal Rx message buffers, the mask bits affect the ID filter programmed on the message
buffer. For the Rx FIFO, the mask bits affect all bits programmed in the filter table (ID, IDE, RTR).
1: The corresponding bit in the filter is checked against the one received
0: the corresponding bit in the filter is “don’t care”