NXP Semiconductors MPC5644A, Reference Manual, Page: 1211 / 1735

Decimation Filter
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1211
that a word of valid sample data can be available at the same time the flush signal is asserted. In this case
the flush is executed and the sample is processed after the flush.
When ISEL = 0, flush bit M_FLUSH must not be asserted when the input data is a timestamp
(M_CTRL = 10).
When the filter is disabled by the FTYPE[1:0] control bit field, the flush command is not executed.
NOTE
In Cascade Mode, the flush command is forwarded to the next cascaded
block together with the output, after the decimation count. Therefore it is
possible that, in a given moment, the taps of a cascaded block are zeroed
after a flush input, while the following ones still retain the old values.
26.5.10 Soft-reset command description
The Soft-Reset command is requested through the self-negated bit SRES of the DECFILTER_MCR
register and provides the CPU with the capability to initialize the Decimation Filter through the slave-bus
interface. The procedure below must be performed for a software reset when the filter is active:
1. disable filter inputs, writing DECFIL_MCR bit IDIS = 1.
2. poll the register DECFIL_MSR until the bit BSY is 0.
3. repeat the step 2 polling; this is necessary to cover the case when a sample is left in the input buffer.
4. write DECFILTER_MCR bit SRES = 1.
After the software reset is issued, all internal Filter TAP registers, the decimation counter, the integrator
outputs (except DECFILTER_CINTCNT) and the state machine are put in the initial state. The status
register DECFILTER_MSR is also cleared. The Coefficient registers are not affected by the SRES. In case
there is some filter processing, the filter process is aborted and the last sample is discarded. In addition,
data in the input buffer waiting to be processed, and data in the output buffer waiting to be read, are
discarded (the requests of service are cleared). The software reset command has high priority and the BSY
bit is set during its operation.
The configuration registers DECFILTER_MXCR and DECFILTER_MCR are also not affected by a soft
reset, except the bit SRES that is self-negated and is always read as zero.
When in debug or freeze mode, the soft reset is executed but the filter remains in debug or freeze mode.
NOTE
It is recommended to clear the IBIE bit before a software reset, especially if
ISEL changes, in order to avoid unwanted interrupt requests.
NOTE
DMA transfers must not be active during soft reset. Data loss can occur.