NXP Semiconductors MPC5644A, Reference Manual, Page: 1172 / 1735

Decimation Filter
MPC5644A Microcontroller Reference Manual, Rev. 6
1172 Freescale Semiconductor
the data is transferred to the filter tap register’s sub-block and is processed by the filter using the MAC,
the coefficient register, and the control logic sub-blocks. Then the result is returned to the master block by
the PSI TX sub-block. This result is accompanied by the corresponding tag information that provides an
address for the data.
To summarize normal mode, the decimation filter works as a slave block on this second slave-bus line, and
there is a PSI master block such as the eQADC to send and read data. This is illustrated in the application
example in
Section 26.7, Application information .
The decimation filter can also work in a standalone mode. In this mode, the input data is supplied and the
output results are read by the chip core processor (CPU) using status and interrupt signals or DMA
requests.
Mixed modes are also provided, allowing input data fed from the PSI interface, and output results read by
the CPU or DMA, or input fed from CPU or DMA and output directed to the PSI interface.
An integrator unit independently accumulates the values of filter outputs. The integration can be restricted
to time windows defined by hardware signals or software.
Two or more decimation filter blocks can also be configured to work in the cascade mode of operation to
obtain a more complex filtering function. The output result of a filter block is connected to the input of the
next filter by means of a dedicated interface.
All signals in the interface are generated in the system clock domain.
Figure 26-1 is the block diagram for the decimation filter.