NXP Semiconductors MPC5644A, Reference Manual, Page: 1280 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1280 Freescale Semiconductor
30.8.2.12 DSPI DSI Serialization Data Register (DSPI_SDR)
The DSPI_SDR contains the states of the Parallel Input signals. The states of the Parallel Input signals are
latched into the DSPI_SDR on the rising edge of every system clock. The DSPI_SDR is read-only. When
the TXSS bit in the DSPI_DSICR is cleared, the data in the DSPI_SDR is used as the source of the DSI
frames.
16
DCONT
DSI Continuous Peripheral Chip Select Enable
The DCONT bit enables the PCS signals to remain asserted between transfers. The DCONT bit only
affects the PCS signals in DSI master mode. See
Section 30.9.6.5, Continuous selection format , for
details. When TSBC bit is set, DCONT bit has no effect.
0 Return Peripheral Chip Select signals to their inactive state after transfer is complete
1 Keep Peripheral Chip Select signals asserted after transfer is complete
17–19
DSICTAS[0:2]
DSI Clock and Transfer Attributes Select
The DSICTAS field selects which of the DSPI_CTAR registers is used to provide transfer attributes
for DSI frames. The DSICTAS field is used in DSI master mode. In DSI slave mode, the DSPI_CTAR1
is always selected.
20
DMS
Data Match Stop. DMS bit if set stops DSI frames transmissions if DDIF flag is set in the DSPI_SR
register.
0 DDIF flag does not have effect on DSI frames transmissions.
1 DDIF flag stops DSI frame transmissions.
21
PES
Parity Error Stop. PES bit if set stops DSI operation if the parity error had happened in received DSI
frame.
0 parity error does not stop DSI frame transmissions.
1 parity error stops all DSI frame transmissions
22
PE
Parity Enable. PE bit enables parity bit transmission and parity reception check for the DSI frames
0 No parity bit included/checked.
1 Parity bit is transmitted instead of last data bit in frame, parity checked for received frame
23
PP
Parity Polarity. PP bit controls polarity of the parity bit transmitted and checked
0 Even Parity: number of “1” bits in the transmitted frame is even. The DSPI_SR[DPEF] bit is set if
in the received frame number of “1” bits is odd.
1 Odd Parity: number of “1” bits in the transmitted frame is odd. The DSPI_SR[DPEF] bit is set if in
the received frame number of “1” bits is even
24–31
DPCS x
DSI Peripheral Chip Select 0–7
The DPCS bits select which of the PCS signals to assert during a DSI master mode transfer.
0 Negate PCS[x]
1 Assert PCS[x]
Table 30-19. DSPI_DSICR field description (continued)
Field Description