NXP Semiconductors MPC5644A, Reference Manual, Page: 344 / 1735

Interrupt Controller (INTC)
MPC5644A Microcontroller Reference Manual, Rev. 6
344 Freescale Semiconductor
Figure 15-3. Program Flow–Software Vector Mode
N is the largest vector number (485) with the greatest hexadecimal address (IVPR + 0x1D90) that is
available in the interrupt memory map for this device. As memory blocks throughout the total memory
map are used for other purposes, the maximum vector number does not indicate the total number of
available interrupt sources for this device.
The total number of entries in the interrupt memory map on this device is 486: 279 peripheral IRQs, 8
software configurable IRQs, and 199 reserved.
In hardware vector mode, the core branches to an interrupt exception handler unique for each interrupt
request source. Typical program flow for hardware vector mode is shown in
Figure 15-4 .
Figure 15-4. Program Flow–Hardware Vector Mode
The INTC supports a hardware vector mode that reduces the time between assertion of an interrupt and
execution of the service routine. It also provides 16 priorities so that lower priority ISRs do not delay the
execution of higher priority ISRs. The priority assigned to each interrupt source is programmable in the
range 0 to 15, with 0 being the lowest and 15 being the highest priority.
ISR ISR 0 address ISR 0
ISR ISR 1
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ISR
ISR n
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ISR
ISR N
ISR n address
ISR N address
ISR 1 address
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Prolog
(Including
using IACKR
to get vector
then bl ISR_n
Epilog
IVPR + IVOR4
IRQ[n]
taken
IACKR
Data Table
Address Instructions Address
VTBA
of Addresses
Prolog b handler 0 handler 0
ISR
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ISR
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Instructions
NOTE:
‘b ISR_n’ is technically
Epilog
Prolog
Epilog
ISR
Prolog
Epilog
handler n
handler N
b handler 1
•
•
•
b handler 2
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•
•
b handler n
b handler N
IVPR + 0x0000
IVPR + 0x0010
IVPR + 0x0020
IVPR + n [0x0010]
Refer to definition of N
IRQ[n]
taken
Address
part of the handler.