NXP Semiconductors MPC5644A, Reference Manual, Page: 465 / 1735

System Integration Unit (SIU)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 465
16.6.15.78.8 Pad Configuration Register 121 (SIU_PCR121)
Figure 16-107. Pad Configuration Register (SIU_PCR121)
16.6.15.78.9 Pad Configuration Register 122 (SIU_PCR122)
Figure 16-108. Pad Configuration Register (SIU_PCR122)
S0x132
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 PA OBE
1
1
The OBE bit must be set to one for both ETPU_A[7] and GPIO[121] when configured as outputs.
IBE
2
2
The IBE bit must be set to one for both ETPU_A[7] and GPIO[121] when configured as inputs. When configured as
ETPU_A[19] or when ETPU_A[7] or GPIO[119] are configured as outputs, the IBE bit may be set to one to reflect
the pin state in the corresponding GPDI register.
0 0 ODE HYS SRC WPE WPS
3
3
The weak pull up/down selection at reset for the ETPU_A[7] pin is determined by the WKPCFG pin.
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 WKP
= Unimplemented or Reserved
Table 16-110. SIU_PCR121 PA values
Signal Name Module Description I/O
1,2
1
In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE
bits. Set IBE = 1 for input or OBE = 1 for output.
2
For I/O functions that change direction dynamically, such as the external data bus, switching between input and
output is handled internally and the IBE and OBE bits are ignored.
PA value
Primary ETPU_A[7] eTPU eTPU channel I/O 0b0001
ALT1 ETPU_A[19] eTPU eTPU channel O 0b0010
ALT2 DSPI_B_SOUT_LVDS

DSPI LVDS

output O 0b0100
ALT3 ETPU_A[6] eTPU eTPU channel O 0b1000
GPIO GPIO[121] SIU GPIO I/O 0b0000
S0x134
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 0 PA OBE
1
1
The OBE bit must be set to one for both ETPU_A[8] and GPIO[122] when configured as outputs.
IBE
2
2
The IBE bit must be set to one for both ETPU_A[8] and GPIO[122] when configured as inputs. When configured as
ETPU_A[20] or when ETPU_A[8] or GPIO[122] are configured as outputs, the IBE bit may be set to one to reflect
the pin state in the corresponding GPDI register.
0 0 ODE HYS SRC WPE WPS
3
3
The weak pull up/down selection at reset for the ETPU_A[8] pin is determined by the WKPCFG pin.
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 WKP
= Unimplemented or Reserved